Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic

Naofumi Homma; Takafumi Aoki; Tatsuo Higuchi

doi:10.1109/ISMVL.2006.10

Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic

Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi

Tohoku Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Citations (Scopus)

Abstract

This paper presents an algorithm-level interpretation of fast adder structures in binary/multiple-valued logic. The key idea is to employ a unified representation of addition algorithms called Counter Tree Diagrams (CTDs). The use of CTDs makes it possible to represent various addition algorithms for any positional number system. In this paper, we introduce an extension of CTDs for representing possible fast addition algorithms with redundant number systems. Using the extended version of CTDs, we can classify the conventional fast adder structures including those using emerging multiple-valued logic devices into three types in a systematic way.

Original language	English
Title of host publication	36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006
Pages	2
Number of pages	1
DOIs	https://doi.org/10.1109/ISMVL.2006.10
Publication status	Published - 2006
Event	36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006 - Singapore, Singapore Duration: 2006 May 17 → 2006 May 20

Publication series

Name	Proceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)	0195-623X

Conference

Conference	36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006
Country/Territory	Singapore
City	Singapore
Period	06/5/17 → 06/5/20

Access to Document

10.1109/ISMVL.2006.10

Cite this

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title = "Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic",

abstract = "This paper presents an algorithm-level interpretation of fast adder structures in binary/multiple-valued logic. The key idea is to employ a unified representation of addition algorithms called Counter Tree Diagrams (CTDs). The use of CTDs makes it possible to represent various addition algorithms for any positional number system. In this paper, we introduce an extension of CTDs for representing possible fast addition algorithms with redundant number systems. Using the extended version of CTDs, we can classify the conventional fast adder structures including those using emerging multiple-valued logic devices into three types in a systematic way.",

author = "Naofumi Homma and Takafumi Aoki and Tatsuo Higuchi",

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series = "Proceedings of The International Symposium on Multiple-Valued Logic",

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Homma, N , Aoki, T & Higuchi, T 2006, Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic. in 36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006., 1623954, Proceedings of The International Symposium on Multiple-Valued Logic, pp. 2, 36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006, Singapore, Singapore, 06/5/17. https://doi.org/10.1109/ISMVL.2006.10

Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic. / Homma, Naofumi ; Aoki, Takafumi; Higuchi, Tatsuo.
36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006. 2006. p. 2 1623954 (Proceedings of The International Symposium on Multiple-Valued Logic).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - This paper presents an algorithm-level interpretation of fast adder structures in binary/multiple-valued logic. The key idea is to employ a unified representation of addition algorithms called Counter Tree Diagrams (CTDs). The use of CTDs makes it possible to represent various addition algorithms for any positional number system. In this paper, we introduce an extension of CTDs for representing possible fast addition algorithms with redundant number systems. Using the extended version of CTDs, we can classify the conventional fast adder structures including those using emerging multiple-valued logic devices into three types in a systematic way.

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Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic

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