Algorithm-level optimization of multiple-valued arithmetic circuits using counter tree diagrams

Naofumi Homma; Katsuhiko Degawa; Takafumi Aoki; Tatsuo Higuchi

doi:10.1109/ISMVL.2007.6

Algorithm-level optimization of multiple-valued arithmetic circuits using counter tree diagrams

Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

This paper presents a novel approach to designing multiple-valued arithmetic circuits based on a unified representation of addition algorithms called Counter Tree Diagrams (CTDs). By using CTDs, we can derive possible variations of addition algorithms in a systematic way without using specific knowledge about underlying arithmetic fundamentals. For any weighted number system, we can design the optimal adder structure by trying every possible CTD representation. In this paper, the potential of the CTD-based method is demonstrated through an experimental design of the Redundant-Binary (RB) adder in multiple-valued current-mode logic. We successfully obtained the RB adder that achieves about 32-57% higher performance in terms of power-delay product compared with the conventional designs.

Original language	English
Title of host publication	37th International Symposium on Multiple-Valued Logic, ISMVL 2007
DOIs	https://doi.org/10.1109/ISMVL.2007.6
Publication status	Published - 2007 Sept 3
Event	37th International Symposium on Multiple-Valued Logic, ISMVL 2007 - Oslo, Norway Duration: 2007 May 13 → 2007 May 16

Publication series

Name	Proceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)	0195-623X

Other

Other	37th International Symposium on Multiple-Valued Logic, ISMVL 2007
Country/Territory	Norway
City	Oslo
Period	07/5/13 → 07/5/16

ASJC Scopus subject areas

Computer Science(all)
Mathematics(all)

Access to Document

10.1109/ISMVL.2007.6

Cite this

Algorithm-level optimization of multiple-valued arithmetic circuits using counter tree diagrams. / Homma, Naofumi; Degawa, Katsuhiko; Aoki, Takafumi et al.
37th International Symposium on Multiple-Valued Logic, ISMVL 2007. 2007. 4215954 (Proceedings of The International Symposium on Multiple-Valued Logic).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Homma, N, Degawa, K, Aoki, T & Higuchi, T 2007, Algorithm-level optimization of multiple-valued arithmetic circuits using counter tree diagrams. in 37th International Symposium on Multiple-Valued Logic, ISMVL 2007., 4215954, Proceedings of The International Symposium on Multiple-Valued Logic, 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, Oslo, Norway, 07/5/13. https://doi.org/10.1109/ISMVL.2007.6

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abstract = "This paper presents a novel approach to designing multiple-valued arithmetic circuits based on a unified representation of addition algorithms called Counter Tree Diagrams (CTDs). By using CTDs, we can derive possible variations of addition algorithms in a systematic way without using specific knowledge about underlying arithmetic fundamentals. For any weighted number system, we can design the optimal adder structure by trying every possible CTD representation. In this paper, the potential of the CTD-based method is demonstrated through an experimental design of the Redundant-Binary (RB) adder in multiple-valued current-mode logic. We successfully obtained the RB adder that achieves about 32-57% higher performance in terms of power-delay product compared with the conventional designs.",

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N2 - This paper presents a novel approach to designing multiple-valued arithmetic circuits based on a unified representation of addition algorithms called Counter Tree Diagrams (CTDs). By using CTDs, we can derive possible variations of addition algorithms in a systematic way without using specific knowledge about underlying arithmetic fundamentals. For any weighted number system, we can design the optimal adder structure by trying every possible CTD representation. In this paper, the potential of the CTD-based method is demonstrated through an experimental design of the Redundant-Binary (RB) adder in multiple-valued current-mode logic. We successfully obtained the RB adder that achieves about 32-57% higher performance in terms of power-delay product compared with the conventional designs.

AB - This paper presents a novel approach to designing multiple-valued arithmetic circuits based on a unified representation of addition algorithms called Counter Tree Diagrams (CTDs). By using CTDs, we can derive possible variations of addition algorithms in a systematic way without using specific knowledge about underlying arithmetic fundamentals. For any weighted number system, we can design the optimal adder structure by trying every possible CTD representation. In this paper, the potential of the CTD-based method is demonstrated through an experimental design of the Redundant-Binary (RB) adder in multiple-valued current-mode logic. We successfully obtained the RB adder that achieves about 32-57% higher performance in terms of power-delay product compared with the conventional designs.

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Algorithm-level optimization of multiple-valued arithmetic circuits using counter tree diagrams

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