AMPLE: An adaptive multi-performance processor for low-energy embedded applications

Tohru Ishihara, Seiichiro Yamaguchi, Yuriko Ishitobi, Tadayuki Matsumura, Yuji Kunitake, Yuichiro Oyama, Yusuke Kaneda, Masanori Muroyama, Toshinori Sato

Research output: Contribution to conferencePaperpeer-review

18 Citations (Scopus)


This paper proposes an energy efficient processor which can be used as a design alternative for the dynamic voltage scaling (DVS) processors in embedded system design. The processor consists of multiple PE (processing element) cores and a selective set-associative cache memory. The PE-cores have the same instruction set architecture but differ in their clock speeds and energy consumptions. Only a single PE-core is activated at a time and the other PE-cores are deactivated using clock gating and signal gating techniques. The major advantage over the DVS processors is a small overhead for changing its performance. The gate-level simulation demonstrates that our processor can change its performance within 1.5 microsecond and dissipates about 10 nanojoule while conventional DVS processors need hundreds of microseconds and dissipate a few microjoule for the performance transition [1, 2].

Original languageEnglish
Number of pages6
Publication statusPublished - 2008 Sept 29
Externally publishedYes
Event2008 Symposium on Application Specific Processors, SASP 2008 - Anaheim, CA, United States
Duration: 2008 Jun 82008 Jun 9


Other2008 Symposium on Application Specific Processors, SASP 2008
Country/TerritoryUnited States
CityAnaheim, CA

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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