An Accuracy/Energy-Flexible Configurable Gabor-Filter Chip Based on Stochastic Computation with Dynamic Voltage-Frequency-Length Scaling

This paper introduces an accuracy/energy-flexible configurable 2-D Gabor filter based on stochastic computation, where stochastic bit stream representing information is used. The Gabor filters show a powerful feature extraction capability, but the calculation based on binary computation is complicated. As opposed to traditional memory-based methods that use fixed Gabor coefficients calculated by software in advance, the proposed circuit dynamically generates the coefficients with small hardware, leading to the power-gating capability. For energy-efficient circuits, dynamic voltage-frequency-length scaling (DVFLS) is proposed to match the performance demands depending on situations. DVFLS controls the lengths of the stochastic bit streams with voltage and frequency, which can lower the energy dissipation and/or increase the throughput with a little accuracy loss. The proposed 64 parallel stochastic Gabor-filter chip is fabricated using TSMC 65-nm CMOS technology with a size of 1.79 mm ×1.79 mm. The measurement result shows 4× higher throughput and 4× lower energy than that using a conventional DVFS technique with a 0.391% accuracy loss. Compared with a conventional configurable Gabor filter, the proposed chip achieves a higher throughput/area with more flexibility of the Gabor coefficients.