In this paper, we present an architecture for neuro-hardware that can be realized in circuits of far smaller scale than in the conventional approach. In order to reduce the scale of the circuits, the architecture employs a new method of computing the membrane potential and the sigmoidal function by encapsulating the probabilistic properties into the relative delay between two pulses. The proposed architecture makes it possible to integrate more than 100 neurons in the latest FPGA chip, which is a 13-fold miniaturization compared to the conventional architecture.
|Number of pages
|Electrical Engineering in Japan (English translation of Denki Gakkai Ronbunshi)
|Published - 2002 Jun
- Hardware miniaturization
- Probabilistic coding digital circuit
- Pulsed neuron