TY - JOUR
T1 - An Experimental 4-Mbit CMOS EEPROM with a nand-Structured Cell
AU - Momodomi, Masaki
AU - Yasuoitoh, Y.
AU - Shirota, Riichiro
AU - Iwata, Yoshihisa
AU - Nakayama, Ryozo
AU - Kirisawa, Ryouhei
AU - Tanaka, Tomoharu
AU - Aritome, Seiichi
AU - Endoh, Tetsuo
AU - Ohuchi, Kazunori
AU - Masuoka, Fujio
PY - 1989/10
Y1 - 1989/10
N2 - A 5-V-only high-density (5I2K × 8 bit) electrically erasable and programmable read-only memory (EEPROM) has been designed and fabricated by using a nand-structured cell with 1.0-μm design rules. The average cell area per bit is 12.9 μm2. Block erasing, successive program-ming, and random reading are achieved using a newly developed NAND-cell control circuit. Typical erasing time is 1.0 ms and page-programming time is 4.0 ms, equivalent to 1.0 s/bit. A dynamic sensing system is introduced to sense the small cell current. Typical read access time is 1.6 ps. The die size is 10,7 × 15.3 mm2.
AB - A 5-V-only high-density (5I2K × 8 bit) electrically erasable and programmable read-only memory (EEPROM) has been designed and fabricated by using a nand-structured cell with 1.0-μm design rules. The average cell area per bit is 12.9 μm2. Block erasing, successive program-ming, and random reading are achieved using a newly developed NAND-cell control circuit. Typical erasing time is 1.0 ms and page-programming time is 4.0 ms, equivalent to 1.0 s/bit. A dynamic sensing system is introduced to sense the small cell current. Typical read access time is 1.6 ps. The die size is 10,7 × 15.3 mm2.
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U2 - 10.1109/JSSC.1989.572587
DO - 10.1109/JSSC.1989.572587
M3 - Article
AN - SCOPUS:0024754599
SN - 0018-9200
VL - 24
SP - 1238
EP - 1243
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 5
ER -