An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture

Yoshiya Komatsu; Shota Ishihara; Masanori Hariyama; Michitaka Kameyama

doi:10.1109/ASPDAC.2011.5722311

An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture

Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama

INF - Computer and Mathematical Sciences

Tohoku University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Citation (Scopus)

Abstract

This paper presents an asynchronous FPGA that combines four-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. Four-phase dual-rail encoding is used for small area and low power of function units, while LEDR encoding for high throughput and low power of data transfer. The proposed FPGA is fabricated in the e-Shuttle 65nm CMOS process and operates at 870 MHz. Compared to the synchronous FPGA, the power consumption is reduced by 38% for the workload of 15%.

Original language	English
Title of host publication	2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011
Pages	89-90
Number of pages	2
DOIs	https://doi.org/10.1109/ASPDAC.2011.5722311
Publication status	Published - 2011
Event	2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011 - Yokohama, Japan Duration: 2011 Jan 25 → 2011 Jan 28

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference	2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011
Country/Territory	Japan
City	Yokohama
Period	11/1/25 → 11/1/28

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10.1109/ASPDAC.2011.5722311

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Komatsu, Y., Ishihara, S., Hariyama, M., & Kameyama, M. (2011). An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture. In 2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011 (pp. 89-90). Article 5722311 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2011.5722311

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title = "An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture",

abstract = "This paper presents an asynchronous FPGA that combines four-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. Four-phase dual-rail encoding is used for small area and low power of function units, while LEDR encoding for high throughput and low power of data transfer. The proposed FPGA is fabricated in the e-Shuttle 65nm CMOS process and operates at 870 MHz. Compared to the synchronous FPGA, the power consumption is reduced by 38% for the workload of 15%.",

author = "Yoshiya Komatsu and Shota Ishihara and Masanori Hariyama and Michitaka Kameyama",

year = "2011",

doi = "10.1109/ASPDAC.2011.5722311",

language = "English",

isbn = "9781424475155",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

pages = "89--90",

booktitle = "2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011",

note = "2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011 ; Conference date: 25-01-2011 Through 28-01-2011",

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Komatsu, Y, Ishihara, S, Hariyama, M & Kameyama, M 2011, An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture. in 2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011., 5722311, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 89-90, 2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011, Yokohama, Japan, 11/1/25. https://doi.org/10.1109/ASPDAC.2011.5722311

An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture. / Komatsu, Yoshiya; Ishihara, Shota; Hariyama, Masanori et al.
2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011. 2011. p. 89-90 5722311 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - This paper presents an asynchronous FPGA that combines four-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. Four-phase dual-rail encoding is used for small area and low power of function units, while LEDR encoding for high throughput and low power of data transfer. The proposed FPGA is fabricated in the e-Shuttle 65nm CMOS process and operates at 870 MHz. Compared to the synchronous FPGA, the power consumption is reduced by 38% for the workload of 15%.

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An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture

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