An integrated multi-scroll circuit with floating-gate mosfets

Tetsuya Fujiwara; Yoshihiko Horio; Kazuyuki Aihara

An integrated multi-scroll circuit with floating-gate mosfets

Tetsuya Fujiwara, Yoshihiko Horio, Kazuyuki Aihara

RIEC - Human and Bio Information Systems Division

Research output: Contribution to journal › Conference article › peer-review

12 Citations (Scopus)

Abstract

This paper proposes a multi-scroll circuit that is fast, compact, versatile, and suitable for CMOS implementation. The circuit uses a high-Q CMOS active inductor circuit as a simulated inductor. We use parallel combinations of N-type conductance circuits with floating-gate MOSFETs to create high-order piecewise-linear negative conductances. We integrate the proposed circuit with MOSIS TSMC 0.35 μm CMOS process. HSPICE simulation results and experimental results from the prototype chip are shown.

Original language	English
Pages (from-to)	III180-III183
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	3
Publication status	Published - 2003
Event	Proceedings of the 2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand Duration: 2003 May 25 → 2003 May 28

Cite this

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title = "An integrated multi-scroll circuit with floating-gate mosfets",

abstract = "This paper proposes a multi-scroll circuit that is fast, compact, versatile, and suitable for CMOS implementation. The circuit uses a high-Q CMOS active inductor circuit as a simulated inductor. We use parallel combinations of N-type conductance circuits with floating-gate MOSFETs to create high-order piecewise-linear negative conductances. We integrate the proposed circuit with MOSIS TSMC 0.35 μm CMOS process. HSPICE simulation results and experimental results from the prototype chip are shown.",

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note = "Proceedings of the 2003 IEEE International Symposium on Circuits and Systems ; Conference date: 25-05-2003 Through 28-05-2003",

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AU - Fujiwara, Tetsuya

AU - Horio, Yoshihiko

AU - Aihara, Kazuyuki

PY - 2003

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N2 - This paper proposes a multi-scroll circuit that is fast, compact, versatile, and suitable for CMOS implementation. The circuit uses a high-Q CMOS active inductor circuit as a simulated inductor. We use parallel combinations of N-type conductance circuits with floating-gate MOSFETs to create high-order piecewise-linear negative conductances. We integrate the proposed circuit with MOSIS TSMC 0.35 μm CMOS process. HSPICE simulation results and experimental results from the prototype chip are shown.

AB - This paper proposes a multi-scroll circuit that is fast, compact, versatile, and suitable for CMOS implementation. The circuit uses a high-Q CMOS active inductor circuit as a simulated inductor. We use parallel combinations of N-type conductance circuits with floating-gate MOSFETs to create high-order piecewise-linear negative conductances. We integrate the proposed circuit with MOSIS TSMC 0.35 μm CMOS process. HSPICE simulation results and experimental results from the prototype chip are shown.

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M3 - Conference article

AN - SCOPUS:0037745098

SN - 0271-4310

VL - 3

SP - III180-III183

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the 2003 IEEE International Symposium on Circuits and Systems

Y2 - 25 May 2003 through 28 May 2003

ER -

An integrated multi-scroll circuit with floating-gate mosfets

Abstract

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