Analysis and reduction technologies of floating diffusion capacitance in CMOS image sensor for photon-countable sensitivity

In this paper, we describe an analysis methodology of the components of floating diffusion (FD) capacitance (CFD) using the developed test element group (TEG) and propose a CFD reduction technology for photon-countable sensitivity. By analyzing the components of CFD, it was confirmed that the sum of them agreed well with CFD obtained by the photoelectric conversion characteristic in the image sensor and both the gate overlap capacitance and the p-n junction capacitance were large. The CFD reduction technology based on the result of analysis was applied to the FD and pixel source follower (SF). This technology is characterized by omitting lightly doped drain (LDD) implantation process, shallow and low concentration diffusion layer, and non-channel stop. Applying the reduction technology, we designed and fabricated a CMOS image sensor chip using 0.18μm 1-Poly-Si 5-Metal CMOS process technology with pinned photodiode (PD). It exhibited CFD of 0.66fF, conversion gain (CG) of 243μV/e- and input referred noise of 0.46e-rms.