Architecture of a high-performance stereo vision VLSI processor

Masanori Hariyama, Seunghwan Lee, Michitaka Kameyama

Research output: Contribution to journalArticlepeer-review


A motion-stereo VLSI processor is designed with a 0.5 μm single-polysilicon double-metal CMOS processor. The processor occupies 12.8 mm × 10.5 mm for four images of a size 128 × 128 and a window size of 16 × 16. The time required for 3D instrumentation is 2.07 ms. The performance is 16 times faster than that of the special purpose fully-pipelined VLSI processor without the concurrent memory access scheme.

Original languageEnglish
Pages (from-to)329-332
Number of pages4
JournalAdvanced Robotics
Issue number5
Publication statusPublished - 2000


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