Architecture of a low-power FPGA based on self-adaptive voltage control

Shota Ishihara; Zhengfan Xia; Masanori Hariyama; Michitaka Kameyama

doi:10.1109/SOCDC.2009.5423801

Architecture of a low-power FPGA based on self-adaptive voltage control

Shota Ishihara, Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama

INF - Computer and Mathematical Sciences

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Citations (Scopus)

Abstract

This paper presents a low-power FPGA with multiple supply voltages. In the proposed FPGA, the supply voltage of each logic block is self-adaptive to the workload, data path and temperature to minimize the power consumption without system performance degradation. In the self-adaptive voltage control scheme, features of the asynchronous architecture are exploited. The data arrival of the asynchronous architecture can be easily detected by detecting the change of the data's phase. By exploiting this feature, the critical path can be detected in real time. Logic blocks on the non-critical path are autonomously switched to a lower supply voltage to reduce the power consumption.

Original language	English
Title of host publication	2009 International SoC Design Conference, ISOCC 2009
Pages	274-277
Number of pages	4
DOIs	https://doi.org/10.1109/SOCDC.2009.5423801
Publication status	Published - 2009 Dec 1
Event	2009 International SoC Design Conference, ISOCC 2009 - Busan, Korea, Republic of Duration: 2009 Nov 22 → 2009 Nov 24

Publication series

Name	2009 International SoC Design Conference, ISOCC 2009

Other

Other	2009 International SoC Design Conference, ISOCC 2009
Country/Territory	Korea, Republic of
City	Busan
Period	09/11/22 → 09/11/24

Keywords

Asynchronous architecture
Dynamic voltage and frequency scaling
Multiple voltages
Reconfigurable VLSI

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/SOCDC.2009.5423801

Cite this

Ishihara, S, Xia, Z, Hariyama, M & Kameyama, M 2009, Architecture of a low-power FPGA based on self-adaptive voltage control. in 2009 International SoC Design Conference, ISOCC 2009., 5423801, 2009 International SoC Design Conference, ISOCC 2009, pp. 274-277, 2009 International SoC Design Conference, ISOCC 2009, Busan, Korea, Republic of, 09/11/22. https://doi.org/10.1109/SOCDC.2009.5423801

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abstract = "This paper presents a low-power FPGA with multiple supply voltages. In the proposed FPGA, the supply voltage of each logic block is self-adaptive to the workload, data path and temperature to minimize the power consumption without system performance degradation. In the self-adaptive voltage control scheme, features of the asynchronous architecture are exploited. The data arrival of the asynchronous architecture can be easily detected by detecting the change of the data's phase. By exploiting this feature, the critical path can be detected in real time. Logic blocks on the non-critical path are autonomously switched to a lower supply voltage to reduce the power consumption.",

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author = "Shota Ishihara and Zhengfan Xia and Masanori Hariyama and Michitaka Kameyama",

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AU - Ishihara, Shota

AU - Xia, Zhengfan

AU - Hariyama, Masanori

AU - Kameyama, Michitaka

PY - 2009/12/1

Y1 - 2009/12/1

N2 - This paper presents a low-power FPGA with multiple supply voltages. In the proposed FPGA, the supply voltage of each logic block is self-adaptive to the workload, data path and temperature to minimize the power consumption without system performance degradation. In the self-adaptive voltage control scheme, features of the asynchronous architecture are exploited. The data arrival of the asynchronous architecture can be easily detected by detecting the change of the data's phase. By exploiting this feature, the critical path can be detected in real time. Logic blocks on the non-critical path are autonomously switched to a lower supply voltage to reduce the power consumption.

AB - This paper presents a low-power FPGA with multiple supply voltages. In the proposed FPGA, the supply voltage of each logic block is self-adaptive to the workload, data path and temperature to minimize the power consumption without system performance degradation. In the self-adaptive voltage control scheme, features of the asynchronous architecture are exploited. The data arrival of the asynchronous architecture can be easily detected by detecting the change of the data's phase. By exploiting this feature, the critical path can be detected in real time. Logic blocks on the non-critical path are autonomously switched to a lower supply voltage to reduce the power consumption.

KW - Asynchronous architecture

KW - Dynamic voltage and frequency scaling

KW - Multiple voltages

KW - Reconfigurable VLSI

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Architecture of a low-power FPGA based on self-adaptive voltage control

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Keywords

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