Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal

Yoshihiro Nakatani; Masanori Hariyama; Michitaka Kameyama

doi:10.1109/IPDPS.2006.1639467

Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal

Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama

INF - Computer and Mathematical Sciences

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

Multi-context FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. Large amount of memory causes significant overhead in area and power consumption. This paper presents two key technologies. The first is a floating-gate-MOS functional pass gate that merges storage and switching functions area-efficiently. The second is the use of a hybrid multiple-valued/binary context switching signal that eliminates redundancy of a conventional multi-context (MC) switch with high scalability. The transistor count of the proposed MC-switch is reduced to 7% in comparison with that of a SRAM-based one.

Original language	English
Title of host publication	20th International Parallel and Distributed Processing Symposium, IPDPS 2006
Publisher	IEEE Computer Society
ISBN (Print)	1424400546, 9781424400546
DOIs	https://doi.org/10.1109/IPDPS.2006.1639467
Publication status	Published - 2006 Jan 1
Event	20th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2006 - Rhodes Island, Greece Duration: 2006 Apr 25 → 2006 Apr 29

Publication series

Name	20th International Parallel and Distributed Processing Symposium, IPDPS 2006
Volume	2006

Other

Other	20th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2006
Country/Territory	Greece
City	Rhodes Island
Period	06/4/25 → 06/4/29

ASJC Scopus subject areas

Engineering(all)

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10.1109/IPDPS.2006.1639467

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Nakatani, Y., Hariyama, M., & Kameyama, M. (2006). Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal. In 20th International Parallel and Distributed Processing Symposium, IPDPS 2006 [1639467] (20th International Parallel and Distributed Processing Symposium, IPDPS 2006; Vol. 2006). IEEE Computer Society. https://doi.org/10.1109/IPDPS.2006.1639467

Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal. / Nakatani, Yoshihiro; Hariyama, Masanori; Kameyama, Michitaka.

20th International Parallel and Distributed Processing Symposium, IPDPS 2006. IEEE Computer Society, 2006. 1639467 (20th International Parallel and Distributed Processing Symposium, IPDPS 2006; Vol. 2006).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Nakatani, Y, Hariyama, M & Kameyama, M 2006, Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal. in 20th International Parallel and Distributed Processing Symposium, IPDPS 2006., 1639467, 20th International Parallel and Distributed Processing Symposium, IPDPS 2006, vol. 2006, IEEE Computer Society, 20th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2006, Rhodes Island, Greece, 06/4/25. https://doi.org/10.1109/IPDPS.2006.1639467

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AB - Multi-context FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. Large amount of memory causes significant overhead in area and power consumption. This paper presents two key technologies. The first is a floating-gate-MOS functional pass gate that merges storage and switching functions area-efficiently. The second is the use of a hybrid multiple-valued/binary context switching signal that eliminates redundancy of a conventional multi-context (MC) switch with high scalability. The transistor count of the proposed MC-switch is reduced to 7% in comparison with that of a SRAM-based one.

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Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal

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