@inproceedings{4bc2d6bd32994ca2a0a33c87de96dc2a,
title = "Architecture of an FPGA accelerator for LDA-based inference",
abstract = "Latent Dirichlet allocation (LDA) based topic inference is a data classification method, that is used efficiently for extremely large data sets. However, the processing time is very large due to the serial computational behavior of the Markov Chain Monte Carlo method used for the topic inference. We propose a pipelined hardware architecture and memory allocation scheme to accelerate LDA using parallel processing. The proposed architecture is implemented on a reconfigurable hardware called FPGA (field programmable gate array), using OpenCL design environment. According to the experimental results, we achieved maximum speed-up of 2.38 times, while maintaining the same quality compared to the conventional CPU-based implementation.",
keywords = "Data classification, Gibbs sampling, Latent Dirichlet allocation, Machine learning, OpenCL for FPGA",
author = "Taisuke Ono and Waidyasooriya, {Hasitha Muthumala} and Masanori Hariyama and Tsukasa Ishigaki",
note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 18th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing, SNPD 2017 ; Conference date: 26-06-2017 Through 28-06-2017",
year = "2017",
month = aug,
day = "29",
doi = "10.1109/SNPD.2017.8022746",
language = "English",
series = "Proceedings - 18th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing, SNPD 2017",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "357--362",
editor = "Hiroaki Hirata and Nomiya Hiroki and Teruhisa Hochin",
booktitle = "Proceedings - 18th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing, SNPD 2017",
address = "United States",
}