TY - JOUR

T1 - Arithmetic-oriented multiple-valued logic-in-memory VLSI based on current-mode logic

AU - Kaeriyama, Shunichi

AU - Hanyu, Takahiro

AU - Kameyama, Michitaka

PY - 2000

Y1 - 2000

N2 - A new logic-in-memory architecture, in which storage elements are distributed over a current-mode logic-circuit plane by the use of floating-gate MOS transistors, is proposed to realize a compact arithmetic VLSI system. Since not only a storage function but also a voltage-mode linear summation and a voltage-to-current conversion are merged into a single floating-gate MOS transistor, the logic-in-memory VLSI becomes very compact with a high-performance capability. As an example, it is demonstrated that the effective chip area of the proposed four-valued current-mode full adder is reduced to 5% under the same switching speed in comparison with the corresponding binary CMOS implementation.

AB - A new logic-in-memory architecture, in which storage elements are distributed over a current-mode logic-circuit plane by the use of floating-gate MOS transistors, is proposed to realize a compact arithmetic VLSI system. Since not only a storage function but also a voltage-mode linear summation and a voltage-to-current conversion are merged into a single floating-gate MOS transistor, the logic-in-memory VLSI becomes very compact with a high-performance capability. As an example, it is demonstrated that the effective chip area of the proposed four-valued current-mode full adder is reduced to 5% under the same switching speed in comparison with the corresponding binary CMOS implementation.

UR - http://www.scopus.com/inward/record.url?scp=0033691343&partnerID=8YFLogxK

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M3 - Conference article

AN - SCOPUS:0033691343

SN - 0195-623X

SP - 438

EP - 443

JO - Proceedings of The International Symposium on Multiple-Valued Logic

JF - Proceedings of The International Symposium on Multiple-Valued Logic

T2 - ISMVL'2000 - 30th IEEE International Symposium on Multiple-Valued Logic

Y2 - 23 May 2000 through 25 May 2000

ER -