Asynchronous stochastic decoding of low-density parity-check codes

Naoya Onizawa, Vincent C. Gaudet, Takahiro Hanyu, Warren J. Gross

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

10 Citations (Scopus)


This paper presents an asynchronous scheduling algorithm for high-throughput stochastic low-density parity-check (LDPC) decoders. Stochastic computation provides ultra-low-complexity hardware and can be implemented using binary or multiple-valued logic gates. Using asynchronous control, it also eliminates a global clock signal and therefore eases the worst-case timing restrictions. A timing model of asynchronous-computation behaviours under a 90nm CMOS technology is used to demonstrate that the proposed algorithm with an optimized computation delay properly decodes a regular (1024, 512) LDPC code without the "lock-up" problem that potentially stops decoding before convergence and hence causes loss in coding gain. Based on our models, the proposed scheme achieves up to 7.37x improvement in decoding throughput with comparable BER performance in comparison with performance results of a conventional synchronous stochastic decoder.

Original languageEnglish
Title of host publicationProceedings - IEEE 42nd International Symposium on Multiple-Valued Logic, ISMVL 2012
Number of pages6
Publication statusPublished - 2012
Event42nd IEEE International Symposium on Multiple-Valued Logic, ISMVL 2012 - Victoria, BC, Canada
Duration: 2012 May 142012 May 16

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)0195-623X


Conference42nd IEEE International Symposium on Multiple-Valued Logic, ISMVL 2012
CityVictoria, BC


  • asynchronous circuits
  • circuit implementation
  • communication systems
  • computer arithmetic
  • forward error correction codes
  • iterative decoding
  • soft computing
  • stochastic computation


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