TY - GEN
T1 - Atomically flattening technology at 850°C for Si(100) surface
AU - Li, X.
AU - Suwa, T.
AU - Teramoto, A.
AU - Kuroda, R.
AU - Sugawa, S.
AU - Ohmi, T.
PY - 2010
Y1 - 2010
N2 - We demonstrate a low temperature flattening method for the 200-mm-diameter (100) orientation silicon wafers. By annealing in ultra pure argon ambient at 850°C or above, atomically flat surfaces composed of atomic terraces and steps appear uniformly in the whole 200mm wafer. The width of atomic terrace changes with the off angle of wafer surface. It is found that with the off angle of 0.50° or below, only mono-atomic steps appear on the atomically flat surface, and the terrace widths are almost equal to the calculation values. Moreover, we have found using the vertical furnace the whole 200mm wafer surface can be atomically flattened in shorter time by increasing the argon gas flow rate or the annealing temperature. Furthermore, after annealing at 900°C or below, there is no slip-line defect in the whole wafer. This low temperature flattening method is very suitable to be applied in the LSI manufacturing.
AB - We demonstrate a low temperature flattening method for the 200-mm-diameter (100) orientation silicon wafers. By annealing in ultra pure argon ambient at 850°C or above, atomically flat surfaces composed of atomic terraces and steps appear uniformly in the whole 200mm wafer. The width of atomic terrace changes with the off angle of wafer surface. It is found that with the off angle of 0.50° or below, only mono-atomic steps appear on the atomically flat surface, and the terrace widths are almost equal to the calculation values. Moreover, we have found using the vertical furnace the whole 200mm wafer surface can be atomically flattened in shorter time by increasing the argon gas flow rate or the annealing temperature. Furthermore, after annealing at 900°C or below, there is no slip-line defect in the whole wafer. This low temperature flattening method is very suitable to be applied in the LSI manufacturing.
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U2 - 10.1149/1.3375615
DO - 10.1149/1.3375615
M3 - Conference contribution
AN - SCOPUS:78650570762
SN - 9781566777919
T3 - ECS Transactions
SP - 299
EP - 309
BT - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 6
PB - Electrochemical Society Inc.
ER -