Beyond-binary circuits for signal processing

T. Hanyu, M. Kameyama, T. Higuchi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)


Several basic arithmetic and logic modules based on MVL (multiple-valued logic), including a multiplier and a pattern-matching accelerator, are presented. A micrograph of a 32-b∗32-b SD (signed-digit) multiplier using multiple-valued bidirectional current-mode circuits is shown. Carry propagation during addition and subtraction is limited to one position to the left, providing totally parallel operation. Linear summation is simply by wiring. A mod-7 three-operand multiplier-Adder based on residue arithmetic is also shown. Each residue digit is represented by a multiple-valued coding suitable for highly parallel computation, making it possible to achieve high-speed arithmetic operations. A quaternary nMOS logic-Array chip for high-speed parallel pattern matching in a knowledge-information processing system is also shown. In addition, as an example of multiple-valued VLSI processors, a parallel-structure-based multiple-valued VLSI processor for high-performance digital control is shown.

Original languageEnglish
Title of host publication1993 IEEE International Solid-State Circuits Conference, ISSCC 1993 - Digest of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages2
ISBN (Electronic)0780309871
Publication statusPublished - 1993 Jan 1
Event40th IEEE International Solid-State Circuits Conference, ISSCC 1993 - San Francisco, United States
Duration: 1993 Feb 241993 Feb 26

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)0193-6530


Conference40th IEEE International Solid-State Circuits Conference, ISSCC 1993
Country/TerritoryUnited States
CitySan Francisco

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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