TY - GEN
T1 - Beyond-binary circuits for signal processing
AU - Hanyu, T.
AU - Kameyama, M.
AU - Higuchi, T.
PY - 1993/1/1
Y1 - 1993/1/1
N2 - Several basic arithmetic and logic modules based on MVL (multiple-valued logic), including a multiplier and a pattern-matching accelerator, are presented. A micrograph of a 32-b∗32-b SD (signed-digit) multiplier using multiple-valued bidirectional current-mode circuits is shown. Carry propagation during addition and subtraction is limited to one position to the left, providing totally parallel operation. Linear summation is simply by wiring. A mod-7 three-operand multiplier-Adder based on residue arithmetic is also shown. Each residue digit is represented by a multiple-valued coding suitable for highly parallel computation, making it possible to achieve high-speed arithmetic operations. A quaternary nMOS logic-Array chip for high-speed parallel pattern matching in a knowledge-information processing system is also shown. In addition, as an example of multiple-valued VLSI processors, a parallel-structure-based multiple-valued VLSI processor for high-performance digital control is shown.
AB - Several basic arithmetic and logic modules based on MVL (multiple-valued logic), including a multiplier and a pattern-matching accelerator, are presented. A micrograph of a 32-b∗32-b SD (signed-digit) multiplier using multiple-valued bidirectional current-mode circuits is shown. Carry propagation during addition and subtraction is limited to one position to the left, providing totally parallel operation. Linear summation is simply by wiring. A mod-7 three-operand multiplier-Adder based on residue arithmetic is also shown. Each residue digit is represented by a multiple-valued coding suitable for highly parallel computation, making it possible to achieve high-speed arithmetic operations. A quaternary nMOS logic-Array chip for high-speed parallel pattern matching in a knowledge-information processing system is also shown. In addition, as an example of multiple-valued VLSI processors, a parallel-structure-based multiple-valued VLSI processor for high-performance digital control is shown.
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U2 - 10.1109/ISSCC.1993.280025
DO - 10.1109/ISSCC.1993.280025
M3 - Conference contribution
AN - SCOPUS:85012830175
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 134
EP - 135
BT - 1993 IEEE International Solid-State Circuits Conference, ISSCC 1993 - Digest of Technical Papers
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 40th IEEE International Solid-State Circuits Conference, ISSCC 1993
Y2 - 24 February 1993 through 26 February 1993
ER -