BIST circuit macro using microprogram ROM for LSI memories

Hiroki Koike, Toshio Takeshima, Masahide Takada

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)


We developed an on-chip memory tester macro using a microprogram ROM BIST circuit. Only slight modification of address buffers, data bus I/O circuits and control clock generators of the memory core circuits was required to implement this BIST macro. We fabricated a 1 Mb DRAM with the BIST, and experimental results showed that the measured shmoo plot of VCC versus the cycle time by the BIST closely agreed with that of a memory tester. Disagreement was caused by test address signal set-up time delay and VOH/VOL differences in both test conditions. The BIST macro will be especially useful for design-for-testability of embedded memories.

Original languageEnglish
Pages (from-to)838-844
Number of pages7
JournalIEICE Transactions on Electronics
Issue number7
Publication statusPublished - 1995 Jul


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