Building blocks to use in innovative non-volatile FPGA architecture based on MTJs

Luca Montesi; Zeljko Zilic; Takahiro Hanyu; Daisuke Suzuki

doi:10.1109/ISVLSI.2012.21

Building blocks to use in innovative non-volatile FPGA architecture based on MTJs

Luca Montesi, Zeljko Zilic, Takahiro Hanyu, Daisuke Suzuki

RIEC - Computing System Platforms Division

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Citations (Scopus)

Abstract

This paper addresses the need for a non-volatile reconfigurable FPGA in order to allow for many current applications to transition away from costly ASIC development. It is assumed that an architecture has been selected and needs to be filled with blocks designed at the transistor level. These are to allow for non-volatility by means of magnetic tunnel junction devices (MTJs). Circuit level designs are presented, together with their successful simulations. The blocks are therefore assembled together and electrically sound simulations are presented for a fully functional FPGA of minimal size. Design and testing is carried out in Cadance Virtuoso and Spectre along with the IBM p13 toolkit. The typical parameters of a University of Tohoku MTJ are used in a SPICE model developed by University of Minnesota.

Original language	English
Title of host publication	Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012
Pages	302-307
Number of pages	6
DOIs	https://doi.org/10.1109/ISVLSI.2012.21
Publication status	Published - 2012
Event	2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012 - Amherst, MA, United States Duration: 2012 Aug 19 → 2012 Aug 21

Publication series

Name	Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012

Conference

Conference	2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012
Country/Territory	United States
City	Amherst, MA
Period	12/8/19 → 12/8/21

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10.1109/ISVLSI.2012.21

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Montesi, L., Zilic, Z., Hanyu, T., & Suzuki, D. (2012). Building blocks to use in innovative non-volatile FPGA architecture based on MTJs. In Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012 (pp. 302-307). Article 6296490 (Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012). https://doi.org/10.1109/ISVLSI.2012.21

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title = "Building blocks to use in innovative non-volatile FPGA architecture based on MTJs",

abstract = "This paper addresses the need for a non-volatile reconfigurable FPGA in order to allow for many current applications to transition away from costly ASIC development. It is assumed that an architecture has been selected and needs to be filled with blocks designed at the transistor level. These are to allow for non-volatility by means of magnetic tunnel junction devices (MTJs). Circuit level designs are presented, together with their successful simulations. The blocks are therefore assembled together and electrically sound simulations are presented for a fully functional FPGA of minimal size. Design and testing is carried out in Cadance Virtuoso and Spectre along with the IBM p13 toolkit. The typical parameters of a University of Tohoku MTJ are used in a SPICE model developed by University of Minnesota.",

author = "Luca Montesi and Zeljko Zilic and Takahiro Hanyu and Daisuke Suzuki",

year = "2012",

doi = "10.1109/ISVLSI.2012.21",

language = "English",

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series = "Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012",

pages = "302--307",

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note = "2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012 ; Conference date: 19-08-2012 Through 21-08-2012",

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Montesi, L, Zilic, Z, Hanyu, T & Suzuki, D 2012, Building blocks to use in innovative non-volatile FPGA architecture based on MTJs. in Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012., 6296490, Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012, pp. 302-307, 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012, Amherst, MA, United States, 12/8/19. https://doi.org/10.1109/ISVLSI.2012.21

Building blocks to use in innovative non-volatile FPGA architecture based on MTJs. / Montesi, Luca; Zilic, Zeljko; Hanyu, Takahiro et al.
Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012. 2012. p. 302-307 6296490 (Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Building blocks to use in innovative non-volatile FPGA architecture based on MTJs

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