Burst mode all-digital high-speed clock recovery circuit and block clock recovery scheme

This paper is focused on an all-digital implementation of the high-speed burst mode demodulator for time-division multiple access (TDMA) satellite communication. A clock recovery scheme in a preamble-less burst recovery demodulator is considered which is an item of research and development in recent years. A burst clock recovery scheme is proposed which can be operated at a speed twice higher than the symbol rate. The deterioration due to the error in the clock phase estimation in the burst clock recovery scheme is regarded as a stochastic process, and the effect of the burst signal on the bit error rate is evaluated by the computer simulation. It is shown, as an example, that when the burst clock recovery scheme is applied to the TDMA satellite communication with a burst length of 800 symbols and transmission filter roll-off factor of 0.4, the burst probability is 1 × 10^MIN6 times/burst for the degradation of 0.2 dB of E_b/N₀. In other words, the proposed system affects only slightly the burst loss probability required in the TDMA system.