Capacitance characteristics of low-k low-cost CVD grown polyimide liner for high-density Cu through-Si-via in three-dimensional LSI

Minimization of the parasitic capacitance arising from Cu-through-Si-vias (TSVs) has been rigorously considered in order to enhance the performances of three-dimensional (3D) LSIs. We have systematically investigated the role of chemical vapor deposited (CVD) polyimide (PI) liner in Cu-TSVs in reducing the TSV capacitance. It is confirmed that CVD grown PI greatly helps to reduce the TSV capacitance as compared to the conventional PECVD-SiO₂ liner. In addition to that the presence of very small hysteresis and a negligible flat-band voltage shift along the voltage axis confirms the suitability of PI liner as dielectric in the Cu-TSVs, if it were operated below the bias voltages of +20 V. In over all, the large reduction in capacitance along with the conformal deposition of PI in the TSVs having less than 3 μm-width with aspect ratios greater than 10 reveals that CVD grown PI has the potential application in the future 3D-LSIs with highly scaled TSV.