Challenge of MOS/MTJ-hybrid nonvolatile logic-in-memory architecture in dark-silicon era

Takahiro Hanyu, Daisuke Suzuki, Akira Mochizuki, Masanori Natsui, Naoya Onizawa, Tadahiko Sugibayashi, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

7 Citations (Scopus)

Abstract

In this paper, we present a new architecture-level approach, called "nonvolatile logic-in-memory (NV-LIM) architecture," to solving performance-wall and power-wall problems due to the present CMOS-only-based logic-LSI processors [1]. Figure 1(a) shows a conventional logic LSI chip architecture, where global interconnections between logic and volatile memory modules dominates performance and power dissipation as well as leakage power continuously consumed by volatile memories. In contrast, since nonvolatile storage elements such as magnetic tunnel junction (MTJ) devices are easily distributed over a logic-circuit plane by using a 3D stack structure as shown in Figure 1(b), performance degradation due to intra-chip global wires can be drastically mitigated, which leads to a high- performance, ultra-low-power and highly reliable (or highly resilient) logic LSI.

Original languageEnglish
Title of host publication2014 IEEE International Electron Devices Meeting, IEDM 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages28.2.1-28.2.3
EditionFebruary
ISBN (Electronic)9781479980017
DOIs
Publication statusPublished - 2015 Feb 20
Event2014 60th IEEE International Electron Devices Meeting, IEDM 2014 - San Francisco, United States
Duration: 2014 Dec 152014 Dec 17

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
NumberFebruary
Volume2015-February
ISSN (Print)0163-1918

Conference

Conference2014 60th IEEE International Electron Devices Meeting, IEDM 2014
Country/TerritoryUnited States
CitySan Francisco
Period14/12/1514/12/17

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