Challenges in 3D integration

Mitsumasa Koyanagi; Kang Wook Lee; Takafumi Fukushima; Tetsu Tanaka

doi:10.1149/05303.0237ecst

Challenges in 3D integration

Mitsumasa Koyanagi, Kang Wook Lee, Takafumi Fukushima, Tetsu Tanaka

Tohoku University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Citations (Scopus)

Abstract

Three-dimensional (3D) LSIs using TSVs are indispensable to achieve high performance and low power LSIs with smaller form factor. A wafer-to-wafer (WtW) technology is suitable for stacking chips with high production yield such as DRAM since the overall yield after stacking rapidly decreases as the number of stacking layers increases. The chip-to-wafer (CtW) is suitable for stacking known good dies (KGDs). In addition, chips with different size which are fabricated using different process technologies can be stacked in the CtW technology. The inherent problem in the CtW technology, however, is low production throughput. To solve these problems, we have proposed a new 3D heterogeneous integration technology called a super-chip technology using self-assembly and electrostatic (SAE) bonding method.

Original language	English
Title of host publication	Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 3
Pages	237-244
Number of pages	8
Edition	3
DOIs	https://doi.org/10.1149/05303.0237ecst
Publication status	Published - 2013
Event	International Symposium on Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 3 - 223rd ECS Meeting - Toronto, ON, Canada Duration: 2013 May 12 → 2013 May 17

Publication series

Name	ECS Transactions
Number	3
Volume	53
ISSN (Print)	1938-5862
ISSN (Electronic)	1938-6737

Conference

Conference	International Symposium on Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 3 - 223rd ECS Meeting
Country/Territory	Canada
City	Toronto, ON
Period	13/5/12 → 13/5/17

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title = "Challenges in 3D integration",

abstract = "Three-dimensional (3D) LSIs using TSVs are indispensable to achieve high performance and low power LSIs with smaller form factor. A wafer-to-wafer (WtW) technology is suitable for stacking chips with high production yield such as DRAM since the overall yield after stacking rapidly decreases as the number of stacking layers increases. The chip-to-wafer (CtW) is suitable for stacking known good dies (KGDs). In addition, chips with different size which are fabricated using different process technologies can be stacked in the CtW technology. The inherent problem in the CtW technology, however, is low production throughput. To solve these problems, we have proposed a new 3D heterogeneous integration technology called a super-chip technology using self-assembly and electrostatic (SAE) bonding method.",

author = "Mitsumasa Koyanagi and Lee, {Kang Wook} and Takafumi Fukushima and Tetsu Tanaka",

year = "2013",

doi = "10.1149/05303.0237ecst",

language = "English",

isbn = "9781607683766",

series = "ECS Transactions",

number = "3",

pages = "237--244",

booktitle = "Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 3",

edition = "3",

note = "International Symposium on Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 3 - 223rd ECS Meeting ; Conference date: 12-05-2013 Through 17-05-2013",

}

Koyanagi, M, Lee, KW, Fukushima, T & Tanaka, T 2013, Challenges in 3D integration. in Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 3. 3 edn, ECS Transactions, no. 3, vol. 53, pp. 237-244, International Symposium on Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 3 - 223rd ECS Meeting, Toronto, ON, Canada, 13/5/12. https://doi.org/10.1149/05303.0237ecst

Challenges in 3D integration. / Koyanagi, Mitsumasa; Lee, Kang Wook; Fukushima, Takafumi et al.
Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 3. 3. ed. 2013. p. 237-244 (ECS Transactions; Vol. 53, No. 3).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - Challenges in 3D integration

AU - Koyanagi, Mitsumasa

AU - Lee, Kang Wook

AU - Fukushima, Takafumi

AU - Tanaka, Tetsu

PY - 2013

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N2 - Three-dimensional (3D) LSIs using TSVs are indispensable to achieve high performance and low power LSIs with smaller form factor. A wafer-to-wafer (WtW) technology is suitable for stacking chips with high production yield such as DRAM since the overall yield after stacking rapidly decreases as the number of stacking layers increases. The chip-to-wafer (CtW) is suitable for stacking known good dies (KGDs). In addition, chips with different size which are fabricated using different process technologies can be stacked in the CtW technology. The inherent problem in the CtW technology, however, is low production throughput. To solve these problems, we have proposed a new 3D heterogeneous integration technology called a super-chip technology using self-assembly and electrostatic (SAE) bonding method.

AB - Three-dimensional (3D) LSIs using TSVs are indispensable to achieve high performance and low power LSIs with smaller form factor. A wafer-to-wafer (WtW) technology is suitable for stacking chips with high production yield such as DRAM since the overall yield after stacking rapidly decreases as the number of stacking layers increases. The chip-to-wafer (CtW) is suitable for stacking known good dies (KGDs). In addition, chips with different size which are fabricated using different process technologies can be stacked in the CtW technology. The inherent problem in the CtW technology, however, is low production throughput. To solve these problems, we have proposed a new 3D heterogeneous integration technology called a super-chip technology using self-assembly and electrostatic (SAE) bonding method.

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ER -

Challenges in 3D integration

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