Characterizing Parallel Multipliers for Detecting Hardware Trojans

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This paper presents a new analysis method for estimating the detectability of a hardware trojan (HT) that causes a path delay fault (PDF) to parallel multipliers. The proposed method characterizes a parallel multiplier with the average delay of all paths in a multiplier. We show that the average delay, which is determined by its multiplier structure, has a relation to the HT detectability. The validity of our method is evaluated by an experiment using Monte Carlo tests that measure the detection probabilities of HTs inserted into typical multipliers, and multiple regression analysis. In addition, we demonstrate how the amounts of inserted delay have impacts on the HT detectability. The result shows that, given an inserted delay amount and a multiplier structure, our analysis is useful for estimating the detectability.

Original languageEnglish
Pages (from-to)1815-1831
Number of pages17
JournalIfCoLoG Journal of Logics and their Applications
Issue number9
Publication statusPublished - 2018 Dec


  • Arithmetic algorithms
  • Hardware trojans
  • Multipliers
  • Path delay faults

ASJC Scopus subject areas

  • Applied Mathematics
  • Logic


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