Chip-level TSV integration for rapid prototyping of 3D system LSIs

Kazuyuki Hozawa; Futoshi Furuta; Yuko Hanaoka; Mayu Aoki; Kenichi Takeda; Katsuyuki Sakuma; Kang Wook Lee; Takafumi Fukushima; Mitsumasa Koyanagi

doi:10.1109/3DIC.2012.6262952

Chip-level TSV integration for rapid prototyping of 3D system LSIs

Kazuyuki Hozawa, Futoshi Furuta, Yuko Hanaoka, Mayu Aoki, Kenichi Takeda, Katsuyuki Sakuma, Kang Wook Lee, Takafumi Fukushima, Mitsumasa Koyanagi

ENG - Mechanical Systems Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

For rapid prototyping of system LSIs based on three-dimension (3D) integration using through-silicon-vias (TSVs), a TSV fabrication technology for a diced chip with copper/low-k interconnections (called "chip-level TSV integration") was developed. The two key processes of this technology are uniform substrate thinning in chip form and via-last TSV formation for nanometer-sized copper/low-k interconnection. Chip-level TSV integration will provide rapid prototyping of 3D system LSIs based on various chips with TSVs.

Original language	English
Title of host publication	2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
Publisher	IEEE Computer Society
ISBN (Print)	9781467321891
DOIs	https://doi.org/10.1109/3DIC.2012.6262952
Publication status	Published - 2011
Event	2011 IEEE International 3D Systems Integration Conference, 3DIC 2011 - Osaka, Japan Duration: 2012 Jan 31 → 2012 Feb 2

Publication series

Name	2011 IEEE International 3D Systems Integration Conference, 3DIC 2011

Conference

Conference	2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
Country/Territory	Japan
City	Osaka
Period	12/1/31 → 12/2/2

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10.1109/3DIC.2012.6262952

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Hozawa, K., Furuta, F., Hanaoka, Y., Aoki, M., Takeda, K., Sakuma, K., Lee, K. W., Fukushima, T., & Koyanagi, M. (2011). Chip-level TSV integration for rapid prototyping of 3D system LSIs. In 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011 Article 6262952 (2011 IEEE International 3D Systems Integration Conference, 3DIC 2011). IEEE Computer Society. https://doi.org/10.1109/3DIC.2012.6262952

@inproceedings{41002f486ff4413a8c106ec224b2b89f,

title = "Chip-level TSV integration for rapid prototyping of 3D system LSIs",

abstract = "For rapid prototyping of system LSIs based on three-dimension (3D) integration using through-silicon-vias (TSVs), a TSV fabrication technology for a diced chip with copper/low-k interconnections (called {"}chip-level TSV integration{"}) was developed. The two key processes of this technology are uniform substrate thinning in chip form and via-last TSV formation for nanometer-sized copper/low-k interconnection. Chip-level TSV integration will provide rapid prototyping of 3D system LSIs based on various chips with TSVs.",

author = "Kazuyuki Hozawa and Futoshi Furuta and Yuko Hanaoka and Mayu Aoki and Kenichi Takeda and Katsuyuki Sakuma and Lee, {Kang Wook} and Takafumi Fukushima and Mitsumasa Koyanagi",

year = "2011",

doi = "10.1109/3DIC.2012.6262952",

language = "English",

isbn = "9781467321891",

series = "2011 IEEE International 3D Systems Integration Conference, 3DIC 2011",

publisher = "IEEE Computer Society",

booktitle = "2011 IEEE International 3D Systems Integration Conference, 3DIC 2011",

address = "United States",

note = "2011 IEEE International 3D Systems Integration Conference, 3DIC 2011 ; Conference date: 31-01-2012 Through 02-02-2012",

}

Hozawa, K, Furuta, F, Hanaoka, Y, Aoki, M, Takeda, K, Sakuma, K, Lee, KW, Fukushima, T & Koyanagi, M 2011, Chip-level TSV integration for rapid prototyping of 3D system LSIs. in 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011., 6262952, 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011, IEEE Computer Society, 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011, Osaka, Japan, 12/1/31. https://doi.org/10.1109/3DIC.2012.6262952

Chip-level TSV integration for rapid prototyping of 3D system LSIs. / Hozawa, Kazuyuki; Furuta, Futoshi; Hanaoka, Yuko et al.
2011 IEEE International 3D Systems Integration Conference, 3DIC 2011. IEEE Computer Society, 2011. 6262952 (2011 IEEE International 3D Systems Integration Conference, 3DIC 2011).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Chip-level TSV integration for rapid prototyping of 3D system LSIs

AU - Hozawa, Kazuyuki

AU - Furuta, Futoshi

AU - Hanaoka, Yuko

AU - Aoki, Mayu

AU - Takeda, Kenichi

AU - Sakuma, Katsuyuki

AU - Lee, Kang Wook

AU - Fukushima, Takafumi

AU - Koyanagi, Mitsumasa

PY - 2011

Y1 - 2011

N2 - For rapid prototyping of system LSIs based on three-dimension (3D) integration using through-silicon-vias (TSVs), a TSV fabrication technology for a diced chip with copper/low-k interconnections (called "chip-level TSV integration") was developed. The two key processes of this technology are uniform substrate thinning in chip form and via-last TSV formation for nanometer-sized copper/low-k interconnection. Chip-level TSV integration will provide rapid prototyping of 3D system LSIs based on various chips with TSVs.

AB - For rapid prototyping of system LSIs based on three-dimension (3D) integration using through-silicon-vias (TSVs), a TSV fabrication technology for a diced chip with copper/low-k interconnections (called "chip-level TSV integration") was developed. The two key processes of this technology are uniform substrate thinning in chip form and via-last TSV formation for nanometer-sized copper/low-k interconnection. Chip-level TSV integration will provide rapid prototyping of 3D system LSIs based on various chips with TSVs.

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U2 - 10.1109/3DIC.2012.6262952

DO - 10.1109/3DIC.2012.6262952

M3 - Conference contribution

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SN - 9781467321891

T3 - 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011

BT - 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011

PB - IEEE Computer Society

T2 - 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011

Y2 - 31 January 2012 through 2 February 2012

ER -

Chip-level TSV integration for rapid prototyping of 3D system LSIs

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