Chip-to-chip/wafer three-dimensional integration of 2.5 mm-sized neuron and memory chips by via-last approach

M. Murugesan, H. Hashimoto, Jichel Bea, M. Koyanagi, T. Fukushima

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Citation (Scopus)

Abstract

A low thermal budget (= 250 °C) chip-to-chip and chip-to-wafer three-dimensional (3D) integration of application-specific smaller artificial intelligence (AI) chips (2.5 mm x 2.5 mm) with 6 level metal (M#) layers were carried out by using TSV (Through - Si - Via) - last method. Several back-end-of-line processes were carefully optimized, such as multi-die thinning, Ml revealing, protection of revealed Ml during TSV metallization, die-level Cu-chemical mechanical polishing for re-distribution layer formation, and µ-bumping were carefully optimized. The diode parameter evaluation for the chips before and after 3D-integration revealed the successful fabrication of AI module for specific applications.

Original languageEnglish
Title of host publication2021 7th International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages28
Number of pages1
ISBN (Electronic)9781665405676
DOIs
Publication statusPublished - 2021 Oct 5
Event7th International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2021 - Virtual, Online, Japan
Duration: 2021 Oct 52021 Oct 11

Publication series

Name2021 7th International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2021

Conference

Conference7th International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2021
Country/TerritoryJapan
CityVirtual, Online
Period21/10/521/10/11

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