TY - GEN
T1 - CoFeB/MgO based perpendicular magnetic tunnel junctions with stepped structure for symmetrizing different retention times of "0" and "1" information
AU - Miura, K.
AU - Ikeda, S.
AU - Yamanouchi, M.
AU - Yamamoto, H.
AU - Mizunuma, K.
AU - Gan, H. D.
AU - Hayakawa, J.
AU - Koizumi, R.
AU - Matsukura, F.
AU - Ohno, H.
PY - 2011
Y1 - 2011
N2 - We investigated perpendicular magnetic tunnel junctions (p-MTJs) with a stepped structure for spin-transfer torque random access memory (SPRAM). In conventional p-MTJs, the retention time for storing "1" is shorter than that for storing "0," because of the mangetostatic energy difference between the two states caused by dipole interaction. To counter this, one had to develop materials with low magnetization. Here we show, by employing a stepped structure, that the retention time can be made equivalent regardless of the stored information ("0" or "1"), without resorting to the employed materials. This is because this structure reduces the dipole interlayer coupling between two ferromagnetic layers as the diameter difference of the free and reference layers of MTJ increases.
AB - We investigated perpendicular magnetic tunnel junctions (p-MTJs) with a stepped structure for spin-transfer torque random access memory (SPRAM). In conventional p-MTJs, the retention time for storing "1" is shorter than that for storing "0," because of the mangetostatic energy difference between the two states caused by dipole interaction. To counter this, one had to develop materials with low magnetization. Here we show, by employing a stepped structure, that the retention time can be made equivalent regardless of the stored information ("0" or "1"), without resorting to the employed materials. This is because this structure reduces the dipole interlayer coupling between two ferromagnetic layers as the diameter difference of the free and reference layers of MTJ increases.
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M3 - Conference contribution
AN - SCOPUS:80052679970
SN - 9784863481640
T3 - Digest of Technical Papers - Symposium on VLSI Technology
SP - 214
EP - 215
BT - 2011 Symposium on VLSI Technology, VLSIT 2011 - Digest of Technical Papers
T2 - 2011 Symposium on VLSI Technology, VLSIT 2011
Y2 - 14 June 2011 through 16 June 2011
ER -