TY - GEN
T1 - Comparative study of tri-gate- and double-gate-type poly-Si fin-channel split-gate flash memories
AU - Liu, Y. X.
AU - Kamei, T.
AU - Matsukawa, T.
AU - Endo, Kazuhiko
AU - O'uchi, S.
AU - Tsukada, J.
AU - Yamauchi, H.
AU - Ishikawa, Y.
AU - Hayashida, T.
AU - Sakamoto, K.
AU - Ogura, A.
AU - Masahara, M.
PY - 2012/10/12
Y1 - 2012/10/12
N2 - The tri-gate (TG)- and double-gate (DG)-type poly-Si fin-channel split-gate flash memories with a thin n +-poly-Si floating-gate (FG) have successfully been fabricated, and their electrical characteristics including the variations of threshold voltage (Vt) and S-slope have been comparatively investigated. It was experimentally found that better short-channel effect (SCE) immunity, smaller V t variations, and a higher program speed are obtained in the TG-type flash memories than in the DG-type memories. Moreover, it was also confirmed that over-erase is effectively suppressed by split-gate structure.
AB - The tri-gate (TG)- and double-gate (DG)-type poly-Si fin-channel split-gate flash memories with a thin n +-poly-Si floating-gate (FG) have successfully been fabricated, and their electrical characteristics including the variations of threshold voltage (Vt) and S-slope have been comparatively investigated. It was experimentally found that better short-channel effect (SCE) immunity, smaller V t variations, and a higher program speed are obtained in the TG-type flash memories than in the DG-type memories. Moreover, it was also confirmed that over-erase is effectively suppressed by split-gate structure.
UR - http://www.scopus.com/inward/record.url?scp=84867213601&partnerID=8YFLogxK
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U2 - 10.1109/SNW.2012.6243318
DO - 10.1109/SNW.2012.6243318
M3 - Conference contribution
AN - SCOPUS:84867213601
SN - 9781467309943
T3 - 2012 IEEE Silicon Nanoelectronics Workshop, SNW 2012
BT - 2012 IEEE Silicon Nanoelectronics Workshop, SNW 2012
T2 - 2012 17th IEEE Silicon Nanoelectronics Workshop, SNW 2012
Y2 - 10 June 2012 through 11 June 2012
ER -