Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI

Hiromitsu Kimura; Takahiro Hanyu; Michitaka Kameyama; Yoshikazu Fujimori; Takashi Nakamura; Hidemi Takasu

Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI

Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama, Yoshikazu Fujimori, Takashi Nakamura, Hidemi Takasu

RIEC - Computing System Platforms Division

Research output: Contribution to journal › Conference article › peer-review

9 Citations (Scopus)

Abstract

Series connection of two ferroelectric capacitors with complementary stored data allows both switching operations and non-destructive storage. This circuitry, used in a fully parallel 32b CAM, results in a dynamic power reduction by 2/3 and static power reduction by 1/9000 compared to a CMOS implementation using 0.6μm ferroelectric CMOS.

Original language	English
Pages (from-to)	157+160-161+485
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Publication status	Published - 2003
Event	2003 Digest of Technical Papers - , United States Duration: 2003 Feb 9 → 2003 Feb 13

Cite this

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title = "Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI",

abstract = "Series connection of two ferroelectric capacitors with complementary stored data allows both switching operations and non-destructive storage. This circuitry, used in a fully parallel 32b CAM, results in a dynamic power reduction by 2/3 and static power reduction by 1/9000 compared to a CMOS implementation using 0.6μm ferroelectric CMOS.",

author = "Hiromitsu Kimura and Takahiro Hanyu and Michitaka Kameyama and Yoshikazu Fujimori and Takashi Nakamura and Hidemi Takasu",

year = "2003",

language = "English",

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journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

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note = "2003 Digest of Technical Papers ; Conference date: 09-02-2003 Through 13-02-2003",

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T1 - Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI

AU - Kimura, Hiromitsu

AU - Hanyu, Takahiro

AU - Kameyama, Michitaka

AU - Fujimori, Yoshikazu

AU - Nakamura, Takashi

AU - Takasu, Hidemi

PY - 2003

Y1 - 2003

N2 - Series connection of two ferroelectric capacitors with complementary stored data allows both switching operations and non-destructive storage. This circuitry, used in a fully parallel 32b CAM, results in a dynamic power reduction by 2/3 and static power reduction by 1/9000 compared to a CMOS implementation using 0.6μm ferroelectric CMOS.

AB - Series connection of two ferroelectric capacitors with complementary stored data allows both switching operations and non-destructive storage. This circuitry, used in a fully parallel 32b CAM, results in a dynamic power reduction by 2/3 and static power reduction by 1/9000 compared to a CMOS implementation using 0.6μm ferroelectric CMOS.

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M3 - Conference article

AN - SCOPUS:0038306547

SN - 0193-6530

SP - 157+160-161+485

JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

T2 - 2003 Digest of Technical Papers

Y2 - 9 February 2003 through 13 February 2003

ER -

Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI

Abstract

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