TY - JOUR
T1 - Complementary metal-oxide-silicon field-effect-transistors featuring atomically flat gate insulator film/silicon interface
AU - Kuroda, Rihito
AU - Teramoto, Akinobu
AU - Nakao, Yukihisa
AU - Suwa, Tomoyuki
AU - Konda, Masahiro
AU - Hasebe, Rui
AU - Li, Xiang
AU - Isogai, Tatsunori
AU - Tanaka, Hiroaki
AU - Sugawa, Shigetoshi
AU - Ohmi, Tadahiro
PY - 2009/4
Y1 - 2009/4
N2 - In this paper, we demonstrate newly developed process technology to fabricate complementary metal-oxide-silicon field-effect transistors (CMOSFETs) having atomically flat gate insulator film/silicon interface on (100) orientated silicon surface. They include 1,200 °C ultraclean argon ambient annealing technology for surface atomically flattening and radical oxidation technology for device isolation, flatness recovery after ion implantation, and gate insulator formation. The fabricated CMOSFET with atomically flat interface exhibit very high current drivability such as 923 and 538 mA/mm for n-channel MOSFET (nMOS) and p-channel MOSFET (pMOS) at gate length of 100nm when combined with very low resistance source and drain contacts, four orders of magnitude lower 1=f noise characteristics when combined with damage free plasma processes, and one decade longer time dependent dielectric breakdown (TDDB) lifetime in comparison to devices with a conventional flatness. The developed technology effectively improves the performance of the silicon-based CMOS large-scale integrated circuits (LSI).
AB - In this paper, we demonstrate newly developed process technology to fabricate complementary metal-oxide-silicon field-effect transistors (CMOSFETs) having atomically flat gate insulator film/silicon interface on (100) orientated silicon surface. They include 1,200 °C ultraclean argon ambient annealing technology for surface atomically flattening and radical oxidation technology for device isolation, flatness recovery after ion implantation, and gate insulator formation. The fabricated CMOSFET with atomically flat interface exhibit very high current drivability such as 923 and 538 mA/mm for n-channel MOSFET (nMOS) and p-channel MOSFET (pMOS) at gate length of 100nm when combined with very low resistance source and drain contacts, four orders of magnitude lower 1=f noise characteristics when combined with damage free plasma processes, and one decade longer time dependent dielectric breakdown (TDDB) lifetime in comparison to devices with a conventional flatness. The developed technology effectively improves the performance of the silicon-based CMOS large-scale integrated circuits (LSI).
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U2 - 10.1143/JJAP.48.04C048
DO - 10.1143/JJAP.48.04C048
M3 - Article
AN - SCOPUS:77952493438
SN - 0021-4922
VL - 48
JO - Japanese Journal of Applied Physics
JF - Japanese Journal of Applied Physics
IS - 4 PART 2
M1 - 04C048
ER -