Configuration memory size reduction of a dynamically reconfigurable processor based on a register-transfer-level packet data transfer scheme

Yoshichika Fujioka; Michitaka Kameyama

doi:10.1109/ISOCC.2012.6407083

Configuration memory size reduction of a dynamically reconfigurable processor based on a register-transfer-level packet data transfer scheme

Yoshichika Fujioka, Michitaka Kameyama

INF - Computer and Mathematical Sciences

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

A register-transfer-level packet routing scheme is proposed to reduce a configuration memory size of a Dynamically Reconfigurable Processor (DRP). The RT(Register-Transfer)-driven concept makes the configuration memory size very small, because packets are not required to be provided at all the clock cycles. Buffer-less routers can be used to construct a compact DRP, if offline scheduling/allocation is effectively utilized to avoid packet collision. Dynamic reconfiguration of Local Memories (LMs) is also realized by the packet data transfer control. It is evaluated that the packet-routing configuration memory size can be reduced to about 1/10 under the Functional Unit (FU) utilization ratio of 10% in comparison with the conventional DRP.

Original language	English
Title of host publication	ISOCC 2012 - 2012 International SoC Design Conference
Pages	235-238
Number of pages	4
DOIs	https://doi.org/10.1109/ISOCC.2012.6407083
Publication status	Published - 2012
Event	2012 International SoC Design Conference, ISOCC 2012 - Jeju Island, Korea, Republic of Duration: 2012 Nov 4 → 2012 Nov 7

Publication series

Name	ISOCC 2012 - 2012 International SoC Design Conference

Other

Other	2012 International SoC Design Conference, ISOCC 2012
Country/Territory	Korea, Republic of
City	Jeju Island
Period	12/11/4 → 12/11/7

Keywords

configuration memory
dynamic reconfiguration of local memories
dynamically reconfigurable processor
register-transfer-level packet transfer
semi-autonomous packet routing

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/ISOCC.2012.6407083

Cite this

Configuration memory size reduction of a dynamically reconfigurable processor based on a register-transfer-level packet data transfer scheme. / Fujioka, Yoshichika; Kameyama, Michitaka.

ISOCC 2012 - 2012 International SoC Design Conference. 2012. p. 235-238 6407083 (ISOCC 2012 - 2012 International SoC Design Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Fujioka, Y & Kameyama, M 2012, Configuration memory size reduction of a dynamically reconfigurable processor based on a register-transfer-level packet data transfer scheme. in ISOCC 2012 - 2012 International SoC Design Conference., 6407083, ISOCC 2012 - 2012 International SoC Design Conference, pp. 235-238, 2012 International SoC Design Conference, ISOCC 2012, Jeju Island, Korea, Republic of, 12/11/4. https://doi.org/10.1109/ISOCC.2012.6407083

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Configuration memory size reduction of a dynamically reconfigurable processor based on a register-transfer-level packet data transfer scheme

Abstract

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Keywords

ASJC Scopus subject areas

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