Construction and test of the first Belle II SVD ladder implementing the origami chip-on-sensor design

C. Irmler; K. Adamczyk; H. Aihara; C. Angelini; T. Aziz; V. Babu; S. Bacher; S. Bahinipati; E. Barberio; Ti Baroncelli; To Baroncelli; A. K. Basith; G. Batignani; A. Bauer; P. K. Behera; T. Bergauer; S. Bettarini; B. Bhuyan; T. Bilka; F. Bosi; L. Bosisio; A. Bozek; F. Buchsteiner; G. Casarosa; M. Ceccanti; D. Červenkov; S. R. Chendvankar; N. Dash; S. T. Divekar; Z. Doležal; D. Dutta; F. Forti; M. Friedl; R. Frühwirth; K. Hara; T. Higuchi; T. Horiguchi; A. Ishikawa; H. B. Jeon; C. Joo; J. Kandra; K. H. Kang; E. Kato; T. Kawasaki; P. Kodyš; T. Kohriki; S. Koike; M. M. Kolwalkar; P. Kvasnička; L. Lanceri; J. Lettenbicher; M. Maki; P. Mammini; S. N. Mayekar; G. B. Mohanty; S. Mohanty; T. Morii; K. R. Nakamura; Z. Natkaniec; K. Negishi; N. K. Nisar; Y. Onuki; W. Ostrowicz; A. Paladino; E. Paoloni; H. Park; F. Pilo; A. Profeti; K. K. Rao; I. Rashevskaia; G. Rizzo; M. Rozanska; S. Sandilya; J. Sasaki; N. Sato; S. Schultschik; C. Schwanda; Y. Seino; N. Shimizu; J. Stypula; J. Suzuki; S. Tanaka; K. Tanida; G. N. Taylor; R. Thalmeier; R. Thomas; T. Tsuboyama; S. Uozumi; P. Urquijo; L. Vitale; M. Volpi; S. Watanuki; I. J. Watson; J. Webb; J. Wiechczynski; S. Williams; B. Würkner; H. Yamamoto; H. Yin; T. Yoshinobu

doi:10.1088/1748-0221/11/01/C01087

Construction and test of the first Belle II SVD ladder implementing the origami chip-on-sensor design

C. Irmler, K. Adamczyk, H. Aihara, C. Angelini, T. Aziz, V. Babu, S. Bacher, S. Bahinipati, E. Barberio, Ti Baroncelli, To Baroncelli, A. K. Basith, G. Batignani, A. Bauer, P. K. Behera, T. Bergauer, S. Bettarini, B. Bhuyan, T. Bilka, F. BosiL. Bosisio, A. Bozek, F. Buchsteiner, G. Casarosa, M. Ceccanti, D. Červenkov, S. R. Chendvankar, N. Dash, S. T. Divekar, Z. Doležal, D. Dutta, F. Forti, M. Friedl, R. Frühwirth, K. Hara, T. Higuchi, T. Horiguchi, A. Ishikawa, H. B. Jeon, C. Joo, J. Kandra, K. H. Kang, E. Kato, T. Kawasaki, P. Kodyš, T. Kohriki, S. Koike, M. M. Kolwalkar, P. Kvasnička, L. Lanceri, J. Lettenbicher, M. Maki, P. Mammini, S. N. Mayekar, G. B. Mohanty, S. Mohanty, T. Morii, K. R. Nakamura, Z. Natkaniec, K. Negishi, N. K. Nisar, Y. Onuki, W. Ostrowicz, A. Paladino, E. Paoloni, H. Park, F. Pilo, A. Profeti, K. K. Rao, I. Rashevskaia, G. Rizzo, M. Rozanska, S. Sandilya, J. Sasaki, N. Sato, S. Schultschik, C. Schwanda, Y. Seino, N. Shimizu, J. Stypula, J. Suzuki, S. Tanaka, K. Tanida, G. N. Taylor, R. Thalmeier, R. Thomas, T. Tsuboyama, S. Uozumi, P. Urquijo, L. Vitale, M. Volpi, S. Watanuki, I. J. Watson, J. Webb, J. Wiechczynski, S. Williams, B. Würkner, H. Yamamoto, H. Yin, T. Yoshinobu

SCI - Physics

Research output: Contribution to journal › Article › peer-review

7 Citations (Scopus)

Abstract

The Belle II Silicon Vertex Detector comprises four layers of double-sided silicon strip detectors (DSSDs), consisting of ladders with two to five sensors each. All sensors are individually read out by APV25 chips with the Origami chip-on-sensor concept for the central DSSDs of the ladders. The chips sit on flexible circuits that are glued on the top of the sensors. This concept allows a low material budget and an efficient cooling of the chips by a single pipe per ladder. We present the construction of the first SVD ladders and results from precision measurements and electrical tests.

Original language	English
Article number	C01087
Journal	Journal of Instrumentation
Volume	11
Issue number	1
DOIs	https://doi.org/10.1088/1748-0221/11/01/C01087
Publication status	Published - 2016 Jan 29

Keywords

Data acquisition concepts
Detector design and construction technologies and materials
Electronic detector readout concepts (solid-state)
Front-end electronics for detector readout

ASJC Scopus subject areas

Instrumentation
Mathematical Physics

Access to Document

10.1088/1748-0221/11/01/C01087

Cite this

Irmler, C., Adamczyk, K., Aihara, H., Angelini, C., Aziz, T., Babu, V., Bacher, S., Bahinipati, S., Barberio, E., Baroncelli, T., Baroncelli, T., Basith, A. K., Batignani, G., Bauer, A., Behera, P. K., Bergauer, T., Bettarini, S., Bhuyan, B., Bilka, T., ... Yoshinobu, T. (2016). Construction and test of the first Belle II SVD ladder implementing the origami chip-on-sensor design. Journal of Instrumentation, 11(1), [C01087]. https://doi.org/10.1088/1748-0221/11/01/C01087

Irmler, C, Adamczyk, K, Aihara, H, Angelini, C, Aziz, T, Babu, V, Bacher, S, Bahinipati, S, Barberio, E, Baroncelli, T, Baroncelli, T, Basith, AK, Batignani, G, Bauer, A, Behera, PK, Bergauer, T, Bettarini, S, Bhuyan, B, Bilka, T, Bosi, F, Bosisio, L, Bozek, A, Buchsteiner, F, Casarosa, G, Ceccanti, M, Červenkov, D, Chendvankar, SR, Dash, N, Divekar, ST, Doležal, Z, Dutta, D, Forti, F, Friedl, M, Frühwirth, R, Hara, K, Higuchi, T, Horiguchi, T, Ishikawa, A, Jeon, HB, Joo, C, Kandra, J, Kang, KH, Kato, E, Kawasaki, T, Kodyš, P, Kohriki, T, Koike, S, Kolwalkar, MM, Kvasnička, P, Lanceri, L, Lettenbicher, J, Maki, M, Mammini, P, Mayekar, SN, Mohanty, GB, Mohanty, S, Morii, T, Nakamura, KR, Natkaniec, Z, Negishi, K, Nisar, NK, Onuki, Y, Ostrowicz, W, Paladino, A, Paoloni, E, Park, H, Pilo, F, Profeti, A, Rao, KK, Rashevskaia, I, Rizzo, G, Rozanska, M, Sandilya, S, Sasaki, J, Sato, N, Schultschik, S, Schwanda, C, Seino, Y, Shimizu, N, Stypula, J, Suzuki, J, Tanaka, S, Tanida, K, Taylor, GN, Thalmeier, R, Thomas, R, Tsuboyama, T, Uozumi, S, Urquijo, P, Vitale, L, Volpi, M, Watanuki, S, Watson, IJ, Webb, J, Wiechczynski, J, Williams, S, Würkner, B, Yamamoto, H, Yin, H & Yoshinobu, T 2016, 'Construction and test of the first Belle II SVD ladder implementing the origami chip-on-sensor design', Journal of Instrumentation, vol. 11, no. 1, C01087. https://doi.org/10.1088/1748-0221/11/01/C01087

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title = "Construction and test of the first Belle II SVD ladder implementing the origami chip-on-sensor design",

abstract = "The Belle II Silicon Vertex Detector comprises four layers of double-sided silicon strip detectors (DSSDs), consisting of ladders with two to five sensors each. All sensors are individually read out by APV25 chips with the Origami chip-on-sensor concept for the central DSSDs of the ladders. The chips sit on flexible circuits that are glued on the top of the sensors. This concept allows a low material budget and an efficient cooling of the chips by a single pipe per ladder. We present the construction of the first SVD ladders and results from precision measurements and electrical tests.",

keywords = "Data acquisition concepts, Detector design and construction technologies and materials, Electronic detector readout concepts (solid-state), Front-end electronics for detector readout",

author = "C. Irmler and K. Adamczyk and H. Aihara and C. Angelini and T. Aziz and V. Babu and S. Bacher and S. Bahinipati and E. Barberio and Ti Baroncelli and To Baroncelli and Basith, {A. K.} and G. Batignani and A. Bauer and Behera, {P. K.} and T. Bergauer and S. Bettarini and B. Bhuyan and T. Bilka and F. Bosi and L. Bosisio and A. Bozek and F. Buchsteiner and G. Casarosa and M. Ceccanti and D. {\v C}ervenkov and Chendvankar, {S. R.} and N. Dash and Divekar, {S. T.} and Z. Dole{\v z}al and D. Dutta and F. Forti and M. Friedl and R. Fr{\"u}hwirth and K. Hara and T. Higuchi and T. Horiguchi and A. Ishikawa and Jeon, {H. B.} and C. Joo and J. Kandra and Kang, {K. H.} and E. Kato and T. Kawasaki and P. Kody{\v s} and T. Kohriki and S. Koike and Kolwalkar, {M. M.} and P. Kvasni{\v c}ka and L. Lanceri and J. Lettenbicher and M. Maki and P. Mammini and Mayekar, {S. N.} and Mohanty, {G. B.} and S. Mohanty and T. Morii and Nakamura, {K. R.} and Z. Natkaniec and K. Negishi and Nisar, {N. K.} and Y. Onuki and W. Ostrowicz and A. Paladino and E. Paoloni and H. Park and F. Pilo and A. Profeti and Rao, {K. K.} and I. Rashevskaia and G. Rizzo and M. Rozanska and S. Sandilya and J. Sasaki and N. Sato and S. Schultschik and C. Schwanda and Y. Seino and N. Shimizu and J. Stypula and J. Suzuki and S. Tanaka and K. Tanida and Taylor, {G. N.} and R. Thalmeier and R. Thomas and T. Tsuboyama and S. Uozumi and P. Urquijo and L. Vitale and M. Volpi and S. Watanuki and Watson, {I. J.} and J. Webb and J. Wiechczynski and S. Williams and B. W{\"u}rkner and H. Yamamoto and H. Yin and T. Yoshinobu",

note = "Publisher Copyright: {\textcopyright} 2016 IOP Publishing Ltd and Sissa Medialab srl.",

year = "2016",

month = jan,

day = "29",

doi = "10.1088/1748-0221/11/01/C01087",

language = "English",

volume = "11",

journal = "Journal of Instrumentation",

issn = "1748-0221",

publisher = "IOP Publishing Ltd.",

number = "1",

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TY - JOUR

T1 - Construction and test of the first Belle II SVD ladder implementing the origami chip-on-sensor design

AU - Irmler, C.

AU - Adamczyk, K.

AU - Aihara, H.

AU - Angelini, C.

AU - Aziz, T.

AU - Babu, V.

AU - Bacher, S.

AU - Bahinipati, S.

AU - Barberio, E.

AU - Baroncelli, Ti

AU - Baroncelli, To

AU - Basith, A. K.

AU - Batignani, G.

AU - Bauer, A.

AU - Behera, P. K.

AU - Bergauer, T.

AU - Bettarini, S.

AU - Bhuyan, B.

AU - Bilka, T.

AU - Bosi, F.

AU - Bosisio, L.

AU - Bozek, A.

AU - Buchsteiner, F.

AU - Casarosa, G.

AU - Ceccanti, M.

AU - Červenkov, D.

AU - Chendvankar, S. R.

AU - Dash, N.

AU - Divekar, S. T.

AU - Doležal, Z.

AU - Dutta, D.

AU - Forti, F.

AU - Friedl, M.

AU - Frühwirth, R.

AU - Hara, K.

AU - Higuchi, T.

AU - Horiguchi, T.

AU - Ishikawa, A.

AU - Jeon, H. B.

AU - Joo, C.

AU - Kandra, J.

AU - Kang, K. H.

AU - Kato, E.

AU - Kawasaki, T.

AU - Kodyš, P.

AU - Kohriki, T.

AU - Koike, S.

AU - Kolwalkar, M. M.

AU - Kvasnička, P.

AU - Lanceri, L.

AU - Lettenbicher, J.

AU - Maki, M.

AU - Mammini, P.

AU - Mayekar, S. N.

AU - Mohanty, G. B.

AU - Mohanty, S.

AU - Morii, T.

AU - Nakamura, K. R.

AU - Natkaniec, Z.

AU - Negishi, K.

AU - Nisar, N. K.

AU - Onuki, Y.

AU - Ostrowicz, W.

AU - Paladino, A.

AU - Paoloni, E.

AU - Park, H.

AU - Pilo, F.

AU - Profeti, A.

AU - Rao, K. K.

AU - Rashevskaia, I.

AU - Rizzo, G.

AU - Rozanska, M.

AU - Sandilya, S.

AU - Sasaki, J.

AU - Sato, N.

AU - Schultschik, S.

AU - Schwanda, C.

AU - Seino, Y.

AU - Shimizu, N.

AU - Stypula, J.

AU - Suzuki, J.

AU - Tanaka, S.

AU - Tanida, K.

AU - Taylor, G. N.

AU - Thalmeier, R.

AU - Thomas, R.

AU - Tsuboyama, T.

AU - Uozumi, S.

AU - Urquijo, P.

AU - Vitale, L.

AU - Volpi, M.

AU - Watanuki, S.

AU - Watson, I. J.

AU - Webb, J.

AU - Wiechczynski, J.

AU - Williams, S.

AU - Würkner, B.

AU - Yamamoto, H.

AU - Yin, H.

AU - Yoshinobu, T.

PY - 2016/1/29

Y1 - 2016/1/29

N2 - The Belle II Silicon Vertex Detector comprises four layers of double-sided silicon strip detectors (DSSDs), consisting of ladders with two to five sensors each. All sensors are individually read out by APV25 chips with the Origami chip-on-sensor concept for the central DSSDs of the ladders. The chips sit on flexible circuits that are glued on the top of the sensors. This concept allows a low material budget and an efficient cooling of the chips by a single pipe per ladder. We present the construction of the first SVD ladders and results from precision measurements and electrical tests.

AB - The Belle II Silicon Vertex Detector comprises four layers of double-sided silicon strip detectors (DSSDs), consisting of ladders with two to five sensors each. All sensors are individually read out by APV25 chips with the Origami chip-on-sensor concept for the central DSSDs of the ladders. The chips sit on flexible circuits that are glued on the top of the sensors. This concept allows a low material budget and an efficient cooling of the chips by a single pipe per ladder. We present the construction of the first SVD ladders and results from precision measurements and electrical tests.

KW - Data acquisition concepts

KW - Detector design and construction technologies and materials

KW - Electronic detector readout concepts (solid-state)

KW - Front-end electronics for detector readout

UR - http://www.scopus.com/inward/record.url?scp=84957013352&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84957013352&partnerID=8YFLogxK

U2 - 10.1088/1748-0221/11/01/C01087

DO - 10.1088/1748-0221/11/01/C01087

M3 - Article

AN - SCOPUS:84957013352

SN - 1748-0221

VL - 11

JO - Journal of Instrumentation

JF - Journal of Instrumentation

IS - 1

M1 - C01087

ER -

Construction and test of the first Belle II SVD ladder implementing the origami chip-on-sensor design

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Keywords

ASJC Scopus subject areas

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