TY - GEN
T1 - Context-based error correction scheme using recurrent neural network for resilient and efficient intra-chip data transmission
AU - Sugaya, Naoto
AU - Natsui, Masanori
AU - Hanyu, Takahiro
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/7/18
Y1 - 2016/7/18
N2 - An error correction scheme utilizing a brain-inspired learning algorithm, called Recurrent Neural Network (RNN), is proposed for resilient and efficient intra-chip data transmission. RNN has a feature to find partially-clustered time-series data stream from an input data stream and predict the next input data from previous input data stream, which can be utilized for realizing an error correction corresponding to the "context" of the data stream. Through the evaluation of intra-chip data transmission in a general-purpose 32-bit microprocessor, it is demonstrated that the proposed scheme performs 95.9% error reduction with 2-times better data transfer efficiency and 94.2% error reduction with 4-times better data transfer efficiency compared with a conventional error correction scheme.
AB - An error correction scheme utilizing a brain-inspired learning algorithm, called Recurrent Neural Network (RNN), is proposed for resilient and efficient intra-chip data transmission. RNN has a feature to find partially-clustered time-series data stream from an input data stream and predict the next input data from previous input data stream, which can be utilized for realizing an error correction corresponding to the "context" of the data stream. Through the evaluation of intra-chip data transmission in a general-purpose 32-bit microprocessor, it is demonstrated that the proposed scheme performs 95.9% error reduction with 2-times better data transfer efficiency and 94.2% error reduction with 4-times better data transfer efficiency compared with a conventional error correction scheme.
KW - context-based error correction
KW - deep learning
KW - intelligent information processing
KW - recurrent neural network
UR - http://www.scopus.com/inward/record.url?scp=84981309680&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84981309680&partnerID=8YFLogxK
U2 - 10.1109/ISMVL.2016.42
DO - 10.1109/ISMVL.2016.42
M3 - Conference contribution
AN - SCOPUS:84981309680
T3 - Proceedings of The International Symposium on Multiple-Valued Logic
SP - 72
EP - 77
BT - Proceedings - 2016 IEEE 46th International Symposium on Multiple-Valued Logic, ISMVL 2016
PB - IEEE Computer Society
T2 - 46th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2016
Y2 - 18 May 2016 through 20 May 2016
ER -