Cost-effective low V_tNi-FUSI CMOS on SiON by means of Al implant (pMOS) and Yb+P coimplant (nMOS)

Low V_tNi fully silicided (FUSI) devices are demonstrated making use of Al implantation for pMOS and Yb or Yb+P implantation for nMOS combined with Ni-silicide phase engineering. When Yb(+P) and Al implantation are followed by a high temperature anneal, significant segregation of Yb or Al toward the Ni-FUSI/SiON interface is observed and large V_t shifts of 450 mV (330 mV) and 200 mV are obtained for nMOS NiSi FUSI/SiON devices and pMOS Ni-rich FUSI/SiON devices, respectively, as compared to the undoped reference devices. The V_t shifts are preserved down to the shortest gate lengths. For both Al and Yb, the V_t shifts are explained by the dopants reacting with and modifying the dielectric. Thus, the low V_t dual implantation approach proposed achieves a low-cost "dual dielectric " implementation without the need of dual deposition dielectrics or capping layers. In the case of Yb implantation followed by a high temperature anneal, a significant reduction in the inversion dielectric thickness is observed, indicating that the reaction between Yb and SiON results in the formation of a high-κ dielectric. The Yb diffusion and reaction at the interface can be engineered using a P coimplant.