Data-transfer-aware design of an FPGA-based heterogeneous multicore platform with custom accelerators

Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama

Research output: Contribution to journalArticlepeer-review


For an FPGA-based heterogeneous multicore platform, we present the design methodology to reduce the total processing time considering data-transfer. The reconfigurability of recent FPGAS with hard CPU cores allows us to realize a single-chip heterogeneous processor optimized for a given application. The major problem in designing such heterogeneous processors is data-transfer between CPU cores and accelerator cores. The total processing time with data-transfers is modeled considering the overlap of computation time and data-transfer time, and optimal design parameters are searched for.

Original languageEnglish
Pages (from-to)2658-2669
Number of pages12
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Issue number12
Publication statusPublished - 2015 Dec


  • Custom accelerators
  • FPGA
  • Heterogeneous multicore
  • Reconfigurable architecture


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