Data-transfer-aware design of an FPGA-based heterogeneous multicore platform with custom accelerators

Yasuhiro Takei; Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Michitaka Kameyama

doi:10.1587/transfun.E98.A.2658

Data-transfer-aware design of an FPGA-based heterogeneous multicore platform with custom accelerators

Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama

INF - Computer and Mathematical Sciences

Tohoku University

Research output: Contribution to journal › Article › peer-review

Abstract

For an FPGA-based heterogeneous multicore platform, we present the design methodology to reduce the total processing time considering data-transfer. The reconfigurability of recent FPGAS with hard CPU cores allows us to realize a single-chip heterogeneous processor optimized for a given application. The major problem in designing such heterogeneous processors is data-transfer between CPU cores and accelerator cores. The total processing time with data-transfers is modeled considering the overlap of computation time and data-transfer time, and optimal design parameters are searched for.

Original language	English
Pages (from-to)	2658-2669
Number of pages	12
Journal	IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Volume	E98A
Issue number	12
DOIs	https://doi.org/10.1587/transfun.E98.A.2658
Publication status	Published - 2015 Dec

Keywords

Custom accelerators
FPGA
Heterogeneous multicore
Reconfigurable architecture

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10.1587/transfun.E98.A.2658

Cite this

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title = "Data-transfer-aware design of an FPGA-based heterogeneous multicore platform with custom accelerators",

abstract = "For an FPGA-based heterogeneous multicore platform, we present the design methodology to reduce the total processing time considering data-transfer. The reconfigurability of recent FPGAS with hard CPU cores allows us to realize a single-chip heterogeneous processor optimized for a given application. The major problem in designing such heterogeneous processors is data-transfer between CPU cores and accelerator cores. The total processing time with data-transfers is modeled considering the overlap of computation time and data-transfer time, and optimal design parameters are searched for.",

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author = "Yasuhiro Takei and Waidyasooriya, {Hasitha Muthumala} and Masanori Hariyama and Michitaka Kameyama",

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Data-transfer-aware design of an FPGA-based heterogeneous multicore platform with custom accelerators. / Takei, Yasuhiro; Waidyasooriya, Hasitha Muthumala ; Hariyama, Masanori et al.
In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E98A, No. 12, 12.2015, p. 2658-2669.

Research output: Contribution to journal › Article › peer-review

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AU - Takei, Yasuhiro

AU - Waidyasooriya, Hasitha Muthumala

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AU - Kameyama, Michitaka

PY - 2015/12

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AB - For an FPGA-based heterogeneous multicore platform, we present the design methodology to reduce the total processing time considering data-transfer. The reconfigurability of recent FPGAS with hard CPU cores allows us to realize a single-chip heterogeneous processor optimized for a given application. The major problem in designing such heterogeneous processors is data-transfer between CPU cores and accelerator cores. The total processing time with data-transfers is modeled considering the overlap of computation time and data-transfer time, and optimal design parameters are searched for.

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Data-transfer-aware design of an FPGA-based heterogeneous multicore platform with custom accelerators

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Keywords

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