Decoupled modified-bit cache

Masafumi Takahashi, Nobuyuki Oba, Hiroaki Kobayashi, Tadao Nakamura

Research output: Contribution to journalConference articlepeer-review


Cache memories are extensively used to reduce memory latency and memory bus traffic. This paper presents a cache memory control mechanism, called Decoupled Modified-bit Cache (DMC), which manages the clean/modified state of cached data in units of bytes to further reduce the bus traffic. Unlike conventional cache memories, the DMC has modified-bit arrays that are separated from a cache tag memory, and uses the modified-bits on demand. The DMC allows a non-fetch allocation on a write miss, cache line fills and replacements in units of bytes, and eliminates unnecessary data transfers. Our simulations with uni-processor and multiprocessor applications indicate that, with 3% more hardware, the DMC reduces the bus traffic and the number of transactions to between 10% and 40% of the levels in a conventional write-back cache memory. It also has strong potential for use in bus-interconnected multiprocessor systems, where the bus traffic dominates the system performance.

Original languageEnglish
Pages (from-to)136-143
Number of pages8
JournalConference Proceedings - International Phoenix Conference on Computers and Communications
Publication statusPublished - 1996
EventProceedings of the 1996 IEEE 15th Annual International Phoenix Conference on Computers and Communications - Scottsdale, AZ, USA
Duration: 1996 Mar 271996 Mar 29


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