Deep-trench etching for chip-to-chip three-dimensional integration technology

Hirokazu Kikuchi, Yusuke Yamada, Hitoshi Kijima, Takafumi Fukushima, Mitsumasa Koyanagi

Research output: Contribution to journalArticlepeer-review

10 Citations (Scopus)


Deep-Si-trench etching was investigated to establish chip-to-chip three-dimensional (3D) integration technology where completed two-dimensional (2D) LSI chips fabricated using standard complementary metal oxide semiconductor (CMOS) technology can be vertically stacked through a number of vertical interconnections formed in the 2D LSI chips. The formation of deep Si trenches through dielectric layers is a key process in chip-to-chip 3D integration technology. In this process, trench profile is an important factor to achieve the complete filling of the resulting deep Si trenches with conductive materials. We have successfully obtained deep Si trenches with a depth of 28 μm through a 7-μm-thick SiO2 layer by inductively coupled plasma (ICP) etching using a time-modulated bias. The desirable high-aspect-ratio Si trenches with a forward tapered shape, a 3.0 μm top width and a 2.4 μm bottom width were also formed in a Si test chip glued on a Si wafer supporting material by the Bosch process.

Original languageEnglish
Pages (from-to)3024-3029
Number of pages6
JournalJapanese Journal of Applied Physics
Issue number4 B
Publication statusPublished - 2006 Apr 25


  • Bosch process
  • Chip-to-chip stacking
  • Deep-Si-trench etching
  • Three-dimensional integration technology
  • Time-modulated bias


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