TY - GEN
T1 - Deep trench etching for through-silicon vias in three-dimensional integration technology
AU - Liang, Jun
AU - Kikuchi, Hirokazu
AU - Konno, Takayuki
AU - Yamada, Yusuke
AU - Fukushima, Takafumi
AU - Tanaka, Tetsu
AU - Koyanagi, Mitsumasa
PY - 2008
Y1 - 2008
N2 - We have developed a deep silicon trench etching process with high aspect ratio for Through-Si-Via (TSV) to fabricate high density 3-D LSIs. Here, we first etched 6-μm-thick SiO2 layer used as a passivation layer to form SiO2 trench with the depth to width ratio of 3:1 by using deep reactive ion etching (DRIE). Then, after a formation process of a fluorocarbon film for sidewall protection, we etched Si to form the Si trench with the depth to width ratio of 20:1 by inductive-coupled plasma (ICP) RIE using a time-modulation method. By employing a modified Bosch method, we formed the SiO2/Si via without side etching underneath SiO2 layer. In this paper, we investigate the effects of etching conditions on etching rate and the resulting via profile, and optimize them for complete filling of conductive materials into the SiO2/Si via. We successfully formed 2 μm TSV with a depth of more than 30 μm through a 6-μm-thick SiO 2 layer. By combining metal vertical interconnection and micro-bump technique, we developed a new 3D integration process.
AB - We have developed a deep silicon trench etching process with high aspect ratio for Through-Si-Via (TSV) to fabricate high density 3-D LSIs. Here, we first etched 6-μm-thick SiO2 layer used as a passivation layer to form SiO2 trench with the depth to width ratio of 3:1 by using deep reactive ion etching (DRIE). Then, after a formation process of a fluorocarbon film for sidewall protection, we etched Si to form the Si trench with the depth to width ratio of 20:1 by inductive-coupled plasma (ICP) RIE using a time-modulation method. By employing a modified Bosch method, we formed the SiO2/Si via without side etching underneath SiO2 layer. In this paper, we investigate the effects of etching conditions on etching rate and the resulting via profile, and optimize them for complete filling of conductive materials into the SiO2/Si via. We successfully formed 2 μm TSV with a depth of more than 30 μm through a 6-μm-thick SiO 2 layer. By combining metal vertical interconnection and micro-bump technique, we developed a new 3D integration process.
KW - Deep Si and SiO trench etching
KW - Three-dimensional integration
KW - Through-silicon via (TSV)
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M3 - Conference contribution
AN - SCOPUS:52349124249
SN - 9789881740816
T3 - Proceedings - Electrochemical Society
SP - 674
EP - 678
BT - Semiconductor Technology, ISTC 2008 - Proceedings of the 7th International Conference on Semiconductor Technology
T2 - 7th International Conference on Semiconductor Technology, ISTC 2008
Y2 - 15 March 2008 through 17 March 2008
ER -