Demonstration of split-gate type trigate flash memory with highly suppressed over-erase

Takahiro Kamei, Yongxun Liu, Takashi Matsukawa, Kazuhiko Endo, Shinichi O'Uchi, Junichi Tsukada, Hiromi Yamauchi, Yuki Ishikawa, Tetsuro Hayashida, Kunihiro Sakamoto, Atsushi Ogura, Meishoku Masahara

Research output: Contribution to journalArticlepeer-review

13 Citations (Scopus)


The functional split-gate type trigate flash memory cell transistors have successfully been fabricated for the first time, and their threshold voltage (V t) variations before and after nor-mode program/erase cycle have systematically been compared with the stack-gate ones. It was experimentally found that split-gate type cell transistors with the same control gate length (L CG) of 176 nm show much smaller V t distribution after erase compared to those of stack-gate ones. Moreover, the measured source-drain breakdown voltage (BV DS) is higher than 3.1 V even the L CG was down to 76 nm. This indicates that the developed split-gate type trigate flash memory is very effective for scaled nor-type flash memory with highly suppressed over-erase.

Original languageEnglish
Article number6145732
Pages (from-to)345-347
Number of pages3
JournalIEEE Electron Device Letters
Issue number3
Publication statusPublished - 2012 Mar
Externally publishedYes


  • Flash memory
  • over-erase
  • split gate
  • trigate

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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