Demonstration of split-gate type trigate flash memory with highly suppressed over-erase

Takahiro Kamei; Yongxun Liu; Takashi Matsukawa; Kazuhiko Endo; Shinichi O'Uchi; Junichi Tsukada; Hiromi Yamauchi; Yuki Ishikawa; Tetsuro Hayashida; Kunihiro Sakamoto; Atsushi Ogura; Meishoku Masahara

doi:10.1109/LED.2011.2181322

Demonstration of split-gate type trigate flash memory with highly suppressed over-erase

Takahiro Kamei, Yongxun Liu, Takashi Matsukawa, Kazuhiko Endo, Shinichi O'Uchi, Junichi Tsukada, Hiromi Yamauchi, Yuki Ishikawa, Tetsuro Hayashida, Kunihiro Sakamoto, Atsushi Ogura, Meishoku Masahara

Research output: Contribution to journal › Article › peer-review

13 Citations (Scopus)

Abstract

The functional split-gate type trigate flash memory cell transistors have successfully been fabricated for the first time, and their threshold voltage (V _t) variations before and after nor-mode program/erase cycle have systematically been compared with the stack-gate ones. It was experimentally found that split-gate type cell transistors with the same control gate length (L _CG) of 176 nm show much smaller V _t distribution after erase compared to those of stack-gate ones. Moreover, the measured source-drain breakdown voltage (BV _DS) is higher than 3.1 V even the L _CG was down to 76 nm. This indicates that the developed split-gate type trigate flash memory is very effective for scaled nor-type flash memory with highly suppressed over-erase.

Original language	English
Article number	6145732
Pages (from-to)	345-347
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	33
Issue number	3
DOIs	https://doi.org/10.1109/LED.2011.2181322
Publication status	Published - 2012 Mar
Externally published	Yes

Keywords

Flash memory
over-erase
split gate
trigate

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/LED.2011.2181322

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@article{a43abded3bf7486e871bd3e3d5a1862f,

title = "Demonstration of split-gate type trigate flash memory with highly suppressed over-erase",

abstract = "The functional split-gate type trigate flash memory cell transistors have successfully been fabricated for the first time, and their threshold voltage (V t) variations before and after nor-mode program/erase cycle have systematically been compared with the stack-gate ones. It was experimentally found that split-gate type cell transistors with the same control gate length (L CG) of 176 nm show much smaller V t distribution after erase compared to those of stack-gate ones. Moreover, the measured source-drain breakdown voltage (BV DS) is higher than 3.1 V even the L CG was down to 76 nm. This indicates that the developed split-gate type trigate flash memory is very effective for scaled nor-type flash memory with highly suppressed over-erase.",

keywords = "Flash memory, over-erase, split gate, trigate",

author = "Takahiro Kamei and Yongxun Liu and Takashi Matsukawa and Kazuhiko Endo and Shinichi O'Uchi and Junichi Tsukada and Hiromi Yamauchi and Yuki Ishikawa and Tetsuro Hayashida and Kunihiro Sakamoto and Atsushi Ogura and Meishoku Masahara",

note = "Funding Information: Manuscript received September 26, 2011; revised December 13, 2011; accepted December 17, 2011. Date of publication February 3, 2012; date of current version February 23, 2012. This work was supported in part by the Nanotechnology Project of NEDO Japan. The review of this letter was arranged by Editor T. Wang. Copyright: Copyright 2012 Elsevier B.V., All rights reserved.",

year = "2012",

month = mar,

doi = "10.1109/LED.2011.2181322",

language = "English",

volume = "33",

pages = "345--347",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "3",

}

TY - JOUR

T1 - Demonstration of split-gate type trigate flash memory with highly suppressed over-erase

AU - Kamei, Takahiro

AU - Liu, Yongxun

AU - Matsukawa, Takashi

AU - Endo, Kazuhiko

AU - O'Uchi, Shinichi

AU - Tsukada, Junichi

AU - Yamauchi, Hiromi

AU - Ishikawa, Yuki

AU - Hayashida, Tetsuro

AU - Sakamoto, Kunihiro

AU - Ogura, Atsushi

AU - Masahara, Meishoku

N1 - Funding Information: Manuscript received September 26, 2011; revised December 13, 2011; accepted December 17, 2011. Date of publication February 3, 2012; date of current version February 23, 2012. This work was supported in part by the Nanotechnology Project of NEDO Japan. The review of this letter was arranged by Editor T. Wang. Copyright: Copyright 2012 Elsevier B.V., All rights reserved.

PY - 2012/3

Y1 - 2012/3

N2 - The functional split-gate type trigate flash memory cell transistors have successfully been fabricated for the first time, and their threshold voltage (V t) variations before and after nor-mode program/erase cycle have systematically been compared with the stack-gate ones. It was experimentally found that split-gate type cell transistors with the same control gate length (L CG) of 176 nm show much smaller V t distribution after erase compared to those of stack-gate ones. Moreover, the measured source-drain breakdown voltage (BV DS) is higher than 3.1 V even the L CG was down to 76 nm. This indicates that the developed split-gate type trigate flash memory is very effective for scaled nor-type flash memory with highly suppressed over-erase.

AB - The functional split-gate type trigate flash memory cell transistors have successfully been fabricated for the first time, and their threshold voltage (V t) variations before and after nor-mode program/erase cycle have systematically been compared with the stack-gate ones. It was experimentally found that split-gate type cell transistors with the same control gate length (L CG) of 176 nm show much smaller V t distribution after erase compared to those of stack-gate ones. Moreover, the measured source-drain breakdown voltage (BV DS) is higher than 3.1 V even the L CG was down to 76 nm. This indicates that the developed split-gate type trigate flash memory is very effective for scaled nor-type flash memory with highly suppressed over-erase.

KW - Flash memory

KW - over-erase

KW - split gate

KW - trigate

UR - http://www.scopus.com/inward/record.url?scp=84862786087&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84862786087&partnerID=8YFLogxK

U2 - 10.1109/LED.2011.2181322

DO - 10.1109/LED.2011.2181322

M3 - Article

AN - SCOPUS:84862786087

SN - 0741-3106

VL - 33

SP - 345

EP - 347

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 3

M1 - 6145732

ER -

Demonstration of split-gate type trigate flash memory with highly suppressed over-erase

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Keywords

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