TY - JOUR
T1 - Design and evaluation of a 54 × 54-bit multiplier based on differential-pair circuitry
AU - Mochizuki, Akira
AU - Shirahama, Hirokatsu
AU - Hanyu, Takahiro
PY - 2007/4
Y1 - 2007/4
N2 - This paper presents a high-speed 54 × 54-bit multiplier using fully differential-pair circuits (DPCs) in 0.18 μm CMOS. The DPC is a key component in maintaining an input signal-voltage swing of 0.2 V while providing a large current-driving capability. The combination of the DPC and the multiple-valued current-mode linear summation makes the critical path shortened and transistor counts reduced. The multiplier has an estimated multiply time of 1.88 ns with 74.2 mW at 400 MHz from a 1.8 V supply occupying a 0.85 mm2 active area.
AB - This paper presents a high-speed 54 × 54-bit multiplier using fully differential-pair circuits (DPCs) in 0.18 μm CMOS. The DPC is a key component in maintaining an input signal-voltage swing of 0.2 V while providing a large current-driving capability. The combination of the DPC and the multiple-valued current-mode linear summation makes the critical path shortened and transistor counts reduced. The multiplier has an estimated multiply time of 1.88 ns with 74.2 mW at 400 MHz from a 1.8 V supply occupying a 0.85 mm2 active area.
KW - Current-mode circuit
KW - Differential-pair circuit
KW - Multiple-valued logic
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U2 - 10.1093/ietele/e90-c.4.683
DO - 10.1093/ietele/e90-c.4.683
M3 - Article
AN - SCOPUS:34247226605
SN - 0916-8524
VL - E90-C
SP - 683
EP - 691
JO - IEICE Transactions on Electronics
JF - IEICE Transactions on Electronics
IS - 4
ER -