TY - GEN
T1 - Design and Evaluation of a Synthesizable Standard-Cell-Based Nonvolatile FPGA
AU - Suzuki, Daisuke
AU - Hanyu, Takahiro
N1 - Funding Information:
This research is supported by CIES consortium program, JST-OPERA Program Grant Number JPMJOP1611, and JST CREST Grant Number JPMJCR19K3, Japan. This research is also supported by VDEC.
Publisher Copyright:
© 2020 IEEE.
PY - 2020/11
Y1 - 2020/11
N2 - A nonvolatile FPGA, where the circuit-configuration information still remains without power supply, offers a powerful solution against the standby power issue. In this paper, a synthesizable nonvolatile FPGA is proposed, where the circuit-configuration information is described in a hardware description language and is pushed through a standard ASIC tool flow with nonvolatile logic circuit IPs such as nonvolatile flip-flops. The use of the ASIC tool flow makes it possible to migrate any arbitrary process technology and to perform architecture-level simulation with physical information. As a typical design example under 55nm CMOS/100nm magnetic tunnel junction (MTJ) technologies, the performance of the proposed nonvolatile FPGA is evaluated in comparison with that of a CMOS-only volatile FPGA.
AB - A nonvolatile FPGA, where the circuit-configuration information still remains without power supply, offers a powerful solution against the standby power issue. In this paper, a synthesizable nonvolatile FPGA is proposed, where the circuit-configuration information is described in a hardware description language and is pushed through a standard ASIC tool flow with nonvolatile logic circuit IPs such as nonvolatile flip-flops. The use of the ASIC tool flow makes it possible to migrate any arbitrary process technology and to perform architecture-level simulation with physical information. As a typical design example under 55nm CMOS/100nm magnetic tunnel junction (MTJ) technologies, the performance of the proposed nonvolatile FPGA is evaluated in comparison with that of a CMOS-only volatile FPGA.
KW - FPGA
KW - Nonvolatile logic
KW - hardware description language
KW - logic synthesis
KW - standard-cell-based design
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U2 - 10.1109/ISMVL49045.2020.000-6
DO - 10.1109/ISMVL49045.2020.000-6
M3 - Conference contribution
AN - SCOPUS:85099789109
T3 - Proceedings of The International Symposium on Multiple-Valued Logic
SP - 194
EP - 199
BT - Proceedings - 2020 IEEE 50th International Symposium on Multiple-Valued Logic, ISMVL 2020
PB - IEEE Computer Society
T2 - 50th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2020
Y2 - 9 November 2020 through 11 November 2020
ER -