In 4‐valued image processing, cellular logic operations can be performed by template or pattern matching. The simplification of the image processing algorithm is discussed using a minimization technique of multiple‐valued logic functions. Furthermore, from the viewpoint of hardware implementation, a new pattern matching scheme is proposed so that two different templates can be processed simultaneously in a pipelining manner. Based on these double pattern matching cells, a compact NMOS image processing chip has been implemented. It is demonstrated that the compactness derives from deduced interconnections in the double pattern matching cells using a quaternary T‐gate realized with pass transistors.