Design and Implementation of Quaternary NMOS Integrated Circuits for Pipelined Image Processing

Michitaka Kameyama, Takahiro Hanyu, Tatsuo Higuchi

Research output: Contribution to journalArticlepeer-review

30 Citations (Scopus)

Abstract

A new pipelined image processor using multiple-valued logic is effectively employed for systematic image processing without encoding and decoding because each pixel can be directly expressed by a single multiple-valued digit for images having several gray levels or several colors. Furthermore, from the viewpoint of hardware implementation, reduction in wiring complexity and reduction in chip area can be achieved in multiple-valued logic system. In this paper, a new pattern matching procedure for performing four-valued image processing based on cellular logic operation is proposed, allowing two different templates to be processed simultaneously in a pipelined manner. Based on these double pattern matching cells, a compact NMOS image processing chip has been implemented. It is demonstrated that the compactness comes from reduced interconnections in the double pattern matching cells using a quaternary multiplexer or T gates, realized with pass transistors and multiple ion implants.

Original languageEnglish
Pages (from-to)20-27
Number of pages8
JournalIEEE Journal of Solid-State Circuits
Volume22
Issue number1
DOIs
Publication statusPublished - 1987 Feb

Fingerprint

Dive into the research topics of 'Design and Implementation of Quaternary NMOS Integrated Circuits for Pipelined Image Processing'. Together they form a unique fingerprint.

Cite this