Design and process integration for high-density, high-speed, and low-power 6F2 cross point MRAM cell

Y. Asao; T. Kajiyama; Y. Fukuzumi; M. Amano; H. Aikawa; T. Ueda; T. Kishi; S. Ikegawa; K. Tsuchida; Y. Iwata; A. Nitayama; K. Shimura; Y. Kato; S. Miura; N. Ishiwata; H. Hada; S. Tahara; H. Yoda

Design and process integration for high-density, high-speed, and low-power 6F² cross point MRAM cell

Y. Asao, T. Kajiyama, Y. Fukuzumi, M. Amano, H. Aikawa, T. Ueda, T. Kishi, S. Ikegawa, K. Tsuchida, Y. Iwata, A. Nitayama, K. Shimura, Y. Kato, S. Miura, N. Ishiwata, H. Hada, S. Tahara, H. Yoda

Research output: Contribution to journal › Conference article › peer-review

16 Citations (Scopus)

Abstract

A new cross point (CP) cell with a hierarchical bit line architecture was proposed for magnetoresistive random access memory (MRAM) (1). The new CP cell has a potential high density of 6F² and a faster access time than the conventional CP cell. A cell layout design to realize 6F² is proposed and associated issues are resolved. Further, a 1Mb MRAM chip based on this structure has been fabricated utilizing 0.13 μm CMOS technology and 0.24×0.48 μm² magnetic tunnel junction (MTJ) sandwiched with the most efficient yoke wires ever reported. The access time of 250 ns and 1.5 V operations are successfully demonstrated with the integrated 1Mb chip.

Original language	English
Pages (from-to)	571-574
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting, IEDM
Publication status	Published - 2004
Externally published	Yes
Event	IEEE International Electron Devices Meeting, 2004 IEDM - San Francisco, CA, United States Duration: 2004 Dec 13 → 2004 Dec 15

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Cite this

Asao, Y., Kajiyama, T., Fukuzumi, Y., Amano, M., Aikawa, H., Ueda, T., Kishi, T., Ikegawa, S., Tsuchida, K., Iwata, Y., Nitayama, A., Shimura, K., Kato, Y., Miura, S., Ishiwata, N., Hada, H., Tahara, S., & Yoda, H. (2004). Design and process integration for high-density, high-speed, and low-power 6F² cross point MRAM cell. Technical Digest - International Electron Devices Meeting, IEDM, 571-574.

Asao, Y, Kajiyama, T, Fukuzumi, Y, Amano, M, Aikawa, H, Ueda, T, Kishi, T, Ikegawa, S, Tsuchida, K, Iwata, Y, Nitayama, A, Shimura, K, Kato, Y, Miura, S, Ishiwata, N, Hada, H, Tahara, S & Yoda, H 2004, 'Design and process integration for high-density, high-speed, and low-power 6F² cross point MRAM cell', Technical Digest - International Electron Devices Meeting, IEDM, pp. 571-574.

@article{0d476948b3254a0da2472c9edfc836f8,

title = "Design and process integration for high-density, high-speed, and low-power 6F2 cross point MRAM cell",

abstract = "A new cross point (CP) cell with a hierarchical bit line architecture was proposed for magnetoresistive random access memory (MRAM) (1). The new CP cell has a potential high density of 6F2 and a faster access time than the conventional CP cell. A cell layout design to realize 6F2 is proposed and associated issues are resolved. Further, a 1Mb MRAM chip based on this structure has been fabricated utilizing 0.13 μm CMOS technology and 0.24×0.48 μm2 magnetic tunnel junction (MTJ) sandwiched with the most efficient yoke wires ever reported. The access time of 250 ns and 1.5 V operations are successfully demonstrated with the integrated 1Mb chip.",

author = "Y. Asao and T. Kajiyama and Y. Fukuzumi and M. Amano and H. Aikawa and T. Ueda and T. Kishi and S. Ikegawa and K. Tsuchida and Y. Iwata and A. Nitayama and K. Shimura and Y. Kato and S. Miura and N. Ishiwata and H. Hada and S. Tahara and H. Yoda",

year = "2004",

language = "English",

pages = "571--574",

journal = "Technical Digest - International Electron Devices Meeting",

issn = "0163-1918",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "IEEE International Electron Devices Meeting, 2004 IEDM ; Conference date: 13-12-2004 Through 15-12-2004",

}

TY - JOUR

T1 - Design and process integration for high-density, high-speed, and low-power 6F2 cross point MRAM cell

AU - Asao, Y.

AU - Kajiyama, T.

AU - Fukuzumi, Y.

AU - Amano, M.

AU - Aikawa, H.

AU - Ueda, T.

AU - Kishi, T.

AU - Ikegawa, S.

AU - Tsuchida, K.

AU - Iwata, Y.

AU - Nitayama, A.

AU - Shimura, K.

AU - Kato, Y.

AU - Miura, S.

AU - Ishiwata, N.

AU - Hada, H.

AU - Tahara, S.

AU - Yoda, H.

PY - 2004

Y1 - 2004

N2 - A new cross point (CP) cell with a hierarchical bit line architecture was proposed for magnetoresistive random access memory (MRAM) (1). The new CP cell has a potential high density of 6F2 and a faster access time than the conventional CP cell. A cell layout design to realize 6F2 is proposed and associated issues are resolved. Further, a 1Mb MRAM chip based on this structure has been fabricated utilizing 0.13 μm CMOS technology and 0.24×0.48 μm2 magnetic tunnel junction (MTJ) sandwiched with the most efficient yoke wires ever reported. The access time of 250 ns and 1.5 V operations are successfully demonstrated with the integrated 1Mb chip.

AB - A new cross point (CP) cell with a hierarchical bit line architecture was proposed for magnetoresistive random access memory (MRAM) (1). The new CP cell has a potential high density of 6F2 and a faster access time than the conventional CP cell. A cell layout design to realize 6F2 is proposed and associated issues are resolved. Further, a 1Mb MRAM chip based on this structure has been fabricated utilizing 0.13 μm CMOS technology and 0.24×0.48 μm2 magnetic tunnel junction (MTJ) sandwiched with the most efficient yoke wires ever reported. The access time of 250 ns and 1.5 V operations are successfully demonstrated with the integrated 1Mb chip.

UR - http://www.scopus.com/inward/record.url?scp=21744455132&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=21744455132&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:21744455132

SN - 0163-1918

SP - 571

EP - 574

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

T2 - IEEE International Electron Devices Meeting, 2004 IEDM

Y2 - 13 December 2004 through 15 December 2004

ER -

Design and process integration for high-density, high-speed, and low-power 6F² cross point MRAM cell

Abstract

ASJC Scopus subject areas

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