Design of a 3-D stacked floating-point Goldschmidt divider

Jubee Tada; Ryusuke Egawa; Hiroaki Kobayashi

doi:10.1109/3DIC.2015.7334598

Design of a 3-D stacked floating-point Goldschmidt divider

Jubee Tada, Ryusuke Egawa, Hiroaki Kobayashi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In the design of 3-D stacked floating-point units, a partitioning method affects the performance and the power consumption. To realize a high-performance and low-power 3-D stacked floating point divider, this paper proposes a circuit partitioning method for the Goldschmidt divider. The proposed partitioning method equalizes the sizes of silicon layers and reduces the number of vertical interconnects. Experimental results show the 3-D stacked Goldschmidt divider which is designed based on the proposed partitioning method achieves an 8.1% critical path delay reduction and a 6.8% average power reduction compared to the 2-D implementation.

Original language	English
Title of host publication	2015 International 3D Systems Integration Conference, 3DIC 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	TS8.28.1-TS8.28.4
ISBN (Electronic)	9781467393850
DOIs	https://doi.org/10.1109/3DIC.2015.7334598
Publication status	Published - 2015 Nov 20
Event	International 3D Systems Integration Conference, 3DIC 2015 - Sendai, Japan Duration: 2015 Aug 31 → 2015 Sept 2

Publication series

Name	2015 International 3D Systems Integration Conference, 3DIC 2015

Other

Other	International 3D Systems Integration Conference, 3DIC 2015
Country/Territory	Japan
City	Sendai
Period	15/8/31 → 15/9/2

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/3DIC.2015.7334598

Cite this

Tada, J., Egawa, R., & Kobayashi, H. (2015). Design of a 3-D stacked floating-point Goldschmidt divider. In 2015 International 3D Systems Integration Conference, 3DIC 2015 (pp. TS8.28.1-TS8.28.4). [7334598] (2015 International 3D Systems Integration Conference, 3DIC 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/3DIC.2015.7334598

Design of a 3-D stacked floating-point Goldschmidt divider. / Tada, Jubee; Egawa, Ryusuke; Kobayashi, Hiroaki.
2015 International 3D Systems Integration Conference, 3DIC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. TS8.28.1-TS8.28.4 7334598 (2015 International 3D Systems Integration Conference, 3DIC 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Tada, J, Egawa, R & Kobayashi, H 2015, Design of a 3-D stacked floating-point Goldschmidt divider. in 2015 International 3D Systems Integration Conference, 3DIC 2015., 7334598, 2015 International 3D Systems Integration Conference, 3DIC 2015, Institute of Electrical and Electronics Engineers Inc., pp. TS8.28.1-TS8.28.4, International 3D Systems Integration Conference, 3DIC 2015, Sendai, Japan, 15/8/31. https://doi.org/10.1109/3DIC.2015.7334598

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abstract = "In the design of 3-D stacked floating-point units, a partitioning method affects the performance and the power consumption. To realize a high-performance and low-power 3-D stacked floating point divider, this paper proposes a circuit partitioning method for the Goldschmidt divider. The proposed partitioning method equalizes the sizes of silicon layers and reduces the number of vertical interconnects. Experimental results show the 3-D stacked Goldschmidt divider which is designed based on the proposed partitioning method achieves an 8.1% critical path delay reduction and a 6.8% average power reduction compared to the 2-D implementation.",

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N2 - In the design of 3-D stacked floating-point units, a partitioning method affects the performance and the power consumption. To realize a high-performance and low-power 3-D stacked floating point divider, this paper proposes a circuit partitioning method for the Goldschmidt divider. The proposed partitioning method equalizes the sizes of silicon layers and reduces the number of vertical interconnects. Experimental results show the 3-D stacked Goldschmidt divider which is designed based on the proposed partitioning method achieves an 8.1% critical path delay reduction and a 6.8% average power reduction compared to the 2-D implementation.

AB - In the design of 3-D stacked floating-point units, a partitioning method affects the performance and the power consumption. To realize a high-performance and low-power 3-D stacked floating point divider, this paper proposes a circuit partitioning method for the Goldschmidt divider. The proposed partitioning method equalizes the sizes of silicon layers and reduces the number of vertical interconnects. Experimental results show the 3-D stacked Goldschmidt divider which is designed based on the proposed partitioning method achieves an 8.1% critical path delay reduction and a 6.8% average power reduction compared to the 2-D implementation.

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Design of a 3-D stacked floating-point Goldschmidt divider

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