TY - GEN
T1 - Design of a low-power MTJ-based true random number generator using a multi-voltage/current converter
AU - Mukaida, Shogo
AU - Onizawa, Naoya
AU - Hanyu, Takahiro
N1 - Funding Information:
ACKNOWLEDGMENT This research is partially supported by the Center of ɹ Innovation Program from Japan Science and Technology Agency, JST. This work is partially supported by MEXT Brainware LSI Project and JSPS KAKENHI Grant Number 16H06300. This work is supported by VLSI Design and Education Center (VDEC), The University of Tokyo with the collaboration with Synopsys Corporation.
Publisher Copyright:
© 2018 IEEE.
PY - 2018/7/19
Y1 - 2018/7/19
N2 - In this paper, we introduce a multi-V/I converter for low-power true random number generator (TRNG) using a three-Terminal magnetic tunnel junction (MTJ) device. As MTJ devices are probabilistically switched by current, the desired probability of 50% is digitally controlled by digital-To-Analog (D/A) and V/I converters. In the conventional MTJ-based TRNG a highly accurate (and large-power) D/A is required to be tolerate to large temperature variation of MTJ devices. By changing the characteristics dynamically according to the temperature variation, the proposed circuit can reduce the bit precision of the D/A converter while generating the quality of random number as the conventional V/I converter. The circuit is designed with a 65nm CMOS/three-Terminal MTJ model, and the simulation is carried out using HSPICE. As a result, the number of bits of the D/A converter is reduced from 10 bits to 7 bits.
AB - In this paper, we introduce a multi-V/I converter for low-power true random number generator (TRNG) using a three-Terminal magnetic tunnel junction (MTJ) device. As MTJ devices are probabilistically switched by current, the desired probability of 50% is digitally controlled by digital-To-Analog (D/A) and V/I converters. In the conventional MTJ-based TRNG a highly accurate (and large-power) D/A is required to be tolerate to large temperature variation of MTJ devices. By changing the characteristics dynamically according to the temperature variation, the proposed circuit can reduce the bit precision of the D/A converter while generating the quality of random number as the conventional V/I converter. The circuit is designed with a 65nm CMOS/three-Terminal MTJ model, and the simulation is carried out using HSPICE. As a result, the number of bits of the D/A converter is reduced from 10 bits to 7 bits.
KW - IoT device
KW - Magnetic tunnel junction
KW - True random number generator
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U2 - 10.1109/ISMVL.2018.00035
DO - 10.1109/ISMVL.2018.00035
M3 - Conference contribution
AN - SCOPUS:85050963170
T3 - Proceedings of The International Symposium on Multiple-Valued Logic
SP - 156
EP - 161
BT - Proceedings - 2018 IEEE 48th International Symposium on Multiple-Valued Logic, ISMVL 2018
PB - IEEE Computer Society
T2 - 48th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2018
Y2 - 16 May 2018 through 18 May 2018
ER -