Design of a multiple-valued VLSI processor for digital control

Katsuhiko Shimabukuro; Michitaka Kameyama; Tatsuo Higuchi

Design of a multiple-valued VLSI processor for digital control

Katsuhiko Shimabukuro, Michitaka Kameyama, Tatsuo Higuchi

INF - Computer and Mathematical Sciences

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

A high-performance parallel, multivalued VLSI processor using the radix-2 signed-digit number system is proposed. Multivalued bidirectional current-mode technology is used not only in the high-speed small-sized arithmetic circuits, but also in reducing the number of connections. Compactness and high-speed operation enhance the performance of the processor chip under the chip size limitation. The processor has been developed for real-time digital control, where the performance is evaluated by delay time. A performance estimation using SPICE simulators shows that the delay time of the processor for operations such as matrix multiplication is greatly reduced in comparison to a conventional binary processor.

Original language	English
Title of host publication	Proceedings of The International Symposium on Multiple-Valued Logic
Publisher	Publ by IEEE
Pages	322-329
Number of pages	8
ISBN (Print)	0818626801
Publication status	Published - 1992 May 1
Event	Proceedings of the 22nd International Symposium on Multiple-Valued Logic - Sendai, Jpn Duration: 1992 May 27 → 1992 May 29

Publication series

Name	Proceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)	0195-623X

Other

Other	Proceedings of the 22nd International Symposium on Multiple-Valued Logic
City	Sendai, Jpn
Period	92/5/27 → 92/5/29

ASJC Scopus subject areas

Computer Science(all)
Mathematics(all)

Cite this

Design of a multiple-valued VLSI processor for digital control. / Shimabukuro, Katsuhiko; Kameyama, Michitaka; Higuchi, Tatsuo.

Proceedings of The International Symposium on Multiple-Valued Logic. Publ by IEEE, 1992. p. 322-329 (Proceedings of The International Symposium on Multiple-Valued Logic).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Shimabukuro, K, Kameyama, M & Higuchi, T 1992, Design of a multiple-valued VLSI processor for digital control. in Proceedings of The International Symposium on Multiple-Valued Logic. Proceedings of The International Symposium on Multiple-Valued Logic, Publ by IEEE, pp. 322-329, Proceedings of the 22nd International Symposium on Multiple-Valued Logic, Sendai, Jpn, 92/5/27.

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Design of a multiple-valued VLSI processor for digital control

Abstract

Publication series

Other

ASJC Scopus subject areas

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