TY - JOUR
T1 - Design of a one-transistor-cell multiple-valued CAM
AU - Hanyu, Takahiro
AU - Kanagawa, Naoki
AU - Kameyama, Michitaka
PY - 1996/11
Y1 - 1996/11
N2 - A new high-density multiple-valued content-addressable memory (CAM) is proposed to perform highly parallel search operations in a limited chip area. The number of cells in the CAM is reduced by the use of multiple-valued data representation. Moreover, multiple-valued stored data correspond to the threshold voltage of a floating-gate MOS transistor, so that the cell circuit can be designed using only a single transistor. As a result, the cell area of the proposed four-valued CAM is reduced to 14% of that of a conventional dynamic binary CAM, and its performance is about 5.4-times higher than that of the corresponding binary one under a 0.8-μm standard EEPROM technology.
AB - A new high-density multiple-valued content-addressable memory (CAM) is proposed to perform highly parallel search operations in a limited chip area. The number of cells in the CAM is reduced by the use of multiple-valued data representation. Moreover, multiple-valued stored data correspond to the threshold voltage of a floating-gate MOS transistor, so that the cell circuit can be designed using only a single transistor. As a result, the cell area of the proposed four-valued CAM is reduced to 14% of that of a conventional dynamic binary CAM, and its performance is about 5.4-times higher than that of the corresponding binary one under a 0.8-μm standard EEPROM technology.
UR - http://www.scopus.com/inward/record.url?scp=0030288846&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0030288846&partnerID=8YFLogxK
U2 - 10.1109/jssc.1996.542311
DO - 10.1109/jssc.1996.542311
M3 - Article
AN - SCOPUS:0030288846
SN - 0018-9200
VL - 31
SP - 1669
EP - 1674
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 11
ER -