Design of a soft-error tolerant 9-transistor/6-magnetic-tunnel-junction hybrid cell based nonvolatile TCAM

This paper introduces a soft-error tolerant ternary content-addressable memory (TCAM) cell based on a transistor/magnetic-tunnel-junction (MTJ) hybrid structure. The MTJ device stores one-bit information as a resistance value and is often used for non-volatile memories. In the proposed nine-transistor (9T)/six-MTJ (6MTJ) cell, one-bit information is redundantly represented using three MTJs to mask a one-bit error per cell that might be occurred due to particle strikes. Thanks to the stackability of the MTJ device over a CMOS layer, there is no area overhead due to the redundancy compared to a conventional 9T-2MTJ cell. A 256-word 64-bit TCAM based on the proposed cell is designed under a 90nm CMOS/MTJ process and is evaluated using HSPICE simulation. The simulation results show that the proposed TCAM properly operates under a one-bit error per cell with comparable energy, area and a 14% delay overhead compared to the conventional TCAM. Compared to a CMOS-based TCAM with an error-correction code that masks a one-bit error per word, the proposed TCAM reduces the nubmer of transistors by 81% while masking a one-bit error per cell.