Design of an 8-nsec 72-bit-parallel-search content-addressable memory using a phase-change device

Satoru Hanzawa; Takahiro Hanyu

doi:10.1587/transele.E94.C.1302

Design of an 8-nsec 72-bit-parallel-search content-addressable memory using a phase-change device

Satoru Hanzawa, Takahiro Hanyu

Systems & Software Division

Research output: Contribution to journal › Article › peer-review

Abstract

This paper presents a content-addressable memory (CAM) using a phase-change device. A hierarchical match-line structure and a one-hot-spot block code are indispensable to suppress the resistance ratio of the phase-change device and the area overhead of match detectors. As a result, an 8-nsec 72-bit-parallel-search CAM is implemented using a phase-change-device/MOS-hybrid circuitry, where high and low resistances are higher than 2.3MΩ and lower than 97 kΩ, respectively, while maintaining one-day retention.

Original language	English
Pages (from-to)	1302-1310
Number of pages	9
Journal	IEICE Transactions on Electronics
Volume	E94-C
Issue number	8
DOIs	https://doi.org/10.1587/transele.E94.C.1302
Publication status	Published - 2011 Aug

Keywords

CAM
Content addressable memory
Nonvolatile memory
One-hot coding
Parallel search
Phasechange device

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1587/transele.E94.C.1302

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@article{204d949aa9d3426090c06ac946e5455a,

title = "Design of an 8-nsec 72-bit-parallel-search content-addressable memory using a phase-change device",

abstract = "This paper presents a content-addressable memory (CAM) using a phase-change device. A hierarchical match-line structure and a one-hot-spot block code are indispensable to suppress the resistance ratio of the phase-change device and the area overhead of match detectors. As a result, an 8-nsec 72-bit-parallel-search CAM is implemented using a phase-change-device/MOS-hybrid circuitry, where high and low resistances are higher than 2.3MΩ and lower than 97 kΩ, respectively, while maintaining one-day retention.",

keywords = "CAM, Content addressable memory, Nonvolatile memory, One-hot coding, Parallel search, Phasechange device",

author = "Satoru Hanzawa and Takahiro Hanyu",

year = "2011",

month = aug,

doi = "10.1587/transele.E94.C.1302",

language = "English",

volume = "E94-C",

pages = "1302--1310",

journal = "IEICE Transactions on Electronics",

issn = "0916-8524",

publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",

number = "8",

}

TY - JOUR

T1 - Design of an 8-nsec 72-bit-parallel-search content-addressable memory using a phase-change device

AU - Hanzawa, Satoru

AU - Hanyu, Takahiro

PY - 2011/8

Y1 - 2011/8

N2 - This paper presents a content-addressable memory (CAM) using a phase-change device. A hierarchical match-line structure and a one-hot-spot block code are indispensable to suppress the resistance ratio of the phase-change device and the area overhead of match detectors. As a result, an 8-nsec 72-bit-parallel-search CAM is implemented using a phase-change-device/MOS-hybrid circuitry, where high and low resistances are higher than 2.3MΩ and lower than 97 kΩ, respectively, while maintaining one-day retention.

AB - This paper presents a content-addressable memory (CAM) using a phase-change device. A hierarchical match-line structure and a one-hot-spot block code are indispensable to suppress the resistance ratio of the phase-change device and the area overhead of match detectors. As a result, an 8-nsec 72-bit-parallel-search CAM is implemented using a phase-change-device/MOS-hybrid circuitry, where high and low resistances are higher than 2.3MΩ and lower than 97 kΩ, respectively, while maintaining one-day retention.

KW - CAM

KW - Content addressable memory

KW - Nonvolatile memory

KW - One-hot coding

KW - Parallel search

KW - Phasechange device

UR - http://www.scopus.com/inward/record.url?scp=79961076717&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=79961076717&partnerID=8YFLogxK

U2 - 10.1587/transele.E94.C.1302

DO - 10.1587/transele.E94.C.1302

M3 - Article

AN - SCOPUS:79961076717

SN - 0916-8524

VL - E94-C

SP - 1302

EP - 1310

JO - IEICE Transactions on Electronics

JF - IEICE Transactions on Electronics

IS - 8

ER -

Design of an 8-nsec 72-bit-parallel-search content-addressable memory using a phase-change device

Abstract

Keywords

ASJC Scopus subject areas

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